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TSC2006IRTJR Folha de dados(PDF) 6 Page - Texas Instruments |
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TSC2006IRTJR Folha de dados(HTML) 6 Page - Texas Instruments |
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6 / 50 page  TIMING INFORMATION BIT0 t DIS(CSR-SDOZ) t H(SDI-SCLKR) NOTE: CPOL=0,CPHA=0,Byte0cyclerequires24SCLKs,andByte1cyclerequireseightSCLKs. t H(SCLKF-SDOVALID) t SU(SDI-SCLKR) t D(CSF-SDOVALID) t SU(SCLKF-CSR) t WH(CS) t C(SCLK) t SU(CSF-SCLK1R) t F t R t WL(SCLK) t WH(SCLK) BIT1 MSBIN MSBOUT CS SS ( ) SCLK SDO(MISO) SDI(MOSI) BIT0 BIT1 TIMING REQUIREMENTS (1) TSC2006 SBAS415C – JUNE 2007 – REVISED MARCH 2009 ......................................................................................................................................................... www.ti.com The TSC2006 supports SPI programming in mode CPOL = 0 and CPHA = 0. The falling edge of SCLK is used to change output (MISO) data and the rising edge is used to latch input (MOSI) data. Eight SCLKs are required to complete the Byte 1 command cycle, and 24 SCLKs are required for the Byte 0 command cycle. CS can stay low during the entire 24 SCLKs of a Byte 0 command cycle, or multiple mixed cycles of reading and writing of bytes and register accesses, as long as the corresponding addresses are supplied. Figure 1. Detailed I/O Timing All specifications typical at –40°C to +85°C, SNSVDD = I/OVDD = 1.6V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN MAX UNIT SNSVDD ≥ 1.6V 10 µs tWL(RESET) (2) Reset low time 1.2V ≤ SNSVDD < 1.6V 13 µs SNSVDD = I/OVDD ≥ 2.7V and ≤ 3.6V, 40 ns 40% to 60% duty cycle SNSVDD = I/OVDD ≥ 1.6V and < 2.7V, tC(SCLK) SPI serial clock cycle time 100 ns 40% to 60% duty cycle SNSVDD = I/OVDD = 1.2V 182 ns 40% to 60% duty cycle SNSVDD = I/OVDD ≥ 2.7V and ≤ 3.6V, 25 MHz 10pF load fSCLK SPI serial clock frequency SNSVDD = I/OVDD ≥ 1.6V and < 2.7V, 10 MHz 10pF load SNSVDD = I/OVDD = 1.2V, 10pF load 5.5 MHz tWH(SCLK) SPI serial clock high time 0.4 × tC(SCLK) 0.6 × tC(SCLK) ns tWL(SCLK) SPI serial clock low time 0.4 × tC(SCLK) 0.6 × tC(SCLK) ns tSU(CSF-SCLK1R) Enable lead time 30 ns tD(CSF-SDOVALID) Slave access time 15 ns tH(SCLKF-SDOVALID) MISO data hold time 6 13 ns tWH(CS) Sequential transfer delay 15 ns tSU(SDI-SCLKR) MOSI data setup time 4 ns tH(SDI-SCLKR) MOSI data hold time 4 ns tDIS(CSR-SDOZ) Slave MISO disable time 15 ns tSU(SCLKF-CSR) Enable lag time 30 ns tR Rise time SNSVDD = I/OVDD = 3V, fSCLK = 25MHz 3 ns tF Fall time SNSVDD = I/OVDD = 3V, fSCLK = 25MHz 3 ns (1) All input signals are specified with tR = tF = 5ns (10% to 90% of I/OVDD) and timed from a voltage level of (VIL + VIH)/2. (2) Refer to Figure 34. 6 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TSC2006 |
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