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CS8405A-IS Folha de dados(PDF) 6 Page - Cirrus Logic |
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CS8405A-IS Folha de dados(HTML) 6 Page - Cirrus Logic |
6 / 36 page CS8405A 6 DS469PP4 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS (TA = 25 °C for suffixes ‘CS’ &’CZ’, TA = -40 to 85°C for ‘IS’ & ‘IZ’ ; VD+ = 5V±10%, VL+ = 3/5V ±5/10%, Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL =20 pF) Notes: 5. The active edge of ISCLK is programmable. 6. The polarity of ILRCK is programmable. 7. No more than 128 SCLK per frame. 8. This delay is to prevent the previous ISCLK edge from being interpreted as the first one after ILRCK has changed. 9. This setup time ensures that this ISCLK edge is interpreted as the first one after ILRCK has changed. Parameter Symbol Min Typ Max Units SDIN Setup Time Before ISCLK Active Edge (Note 5) tds 20 - - ns SDIN Hold Time After ISCLK Active Edge (Note 5) tdh 20 - - ns Master Mode OMCK to ISCLK active edge delay (Note 5) tsmd 0 - 10 ns OMCK to ILRCK delay (Note 6) tlmd 0 - 10 ns ISCLK and ILRCK Duty Cycle - 50 - % Slave Mode ISCLK Period (Note 7) tsckw 36 - - ns ISCLK Input Low Width tsckl 14 - - ns ISCLK Input High Width tsckh 14 - - ns ISCLK Active Edge to ILRCK Edge (Note 5,6,8) tlrckd 20 - - ns ILRCK Edge Setup Before ISCLK Active Edge (Note 5,6,9) tlrcks 20 - - ns ISCLK ILRCK (output) (output) OMCK (input) t smd t lmd sckh sckl sckw t t t (input) (input) SDIN dh t ds t lrcks t lrckd t ISCLK ILRCK Figure 1. Audio Port Master Mode Timing Figure 2. Audio Port Slave Mode and Data Input Timing |
Nº de peça semelhante - CS8405A-IS |
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Descrição semelhante - CS8405A-IS |
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