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MC100EP139DWR2G Folha de dados(PDF) 2 Page - ON Semiconductor |
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MC100EP139DWR2G Folha de dados(HTML) 2 Page - ON Semiconductor |
2 / 14 page MC10EP139, MC100EP139 www.onsemi.com 2 CLK Figure 1. 20-Lead Pinout (Top View) CLK MR VCC Q0 Q1 Q1 Q2 Q2 Q3 Q3 VEE EN VCC Q0 VBB Warning: All VCC and VEE pins must be externally connected to a Power Supply to guarantee proper operation. DIVSELb0 DIVSELb1 DIVSELa VCC MC10/100EP139 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Table 1. PIN DESCRIPTION PIN FUNCTION CLK*, CLK* ECL Differential Clock Inputs EN* ECL Sync Enable MR* ECL Master Reset VBB ECL Reference Output Q0, Q1, Q0, Q1 ECL Differential B2/4 Outputs Q2, Q3, Q2, Q3 ECL Differential B4/5/6 Outputs DIVSELa* ECL Frequency Select Input B2/4 DIVSELb0* ECL Frequency Select Input B4/5/6 DIVSELb1* ECL Frequency Select Input B4/5/6 VCC ECL Positive Supply VEE ECL Negative Supply EP Exposed Pad *Pins will default low when left open. 1 2 3 4 5 15 14 13 12 11 67 8 9 10 20 19 18 17 16 Figure 2. QFN-20 Pinout (Top View) Q1 Q1 Q2 Q2 Q3 CLK CLK MR DIVSELb0 VBB Exposed Pad MC10/100EP139 Warning: All VCC and VEE pins must be externally connected to a Power Supply to guarantee proper operation. The Exposed Pad (EP) on package bottom must be attached to a heat-sinking con- duit. The Exposed Pad may only be electrically connected to VEE. |
Nº de peça semelhante - MC100EP139DWR2G |
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Descrição semelhante - MC100EP139DWR2G |
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