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LM2453 Folha de dados(PDF) 3 Page - National Semiconductor (TI) |
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LM2453 Folha de dados(HTML) 3 Page - National Semiconductor (TI) |
3 / 14 page Absolute Maximum Ratings (Notes 1, 3) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. 80V Voltage, V CC1 +90V 120V Supply V CC2 +130V Bias Voltage, V BB +15V Input Voltage, V IN 0V to 4V V BLANK Input Voltage, VBLANK 0V to V BBV Storage Temperature Range, T STG −65˚C to +150˚C Lead Temperature (Soldering, <10 sec.) 300˚C ESD Tolerance, Human Body Model 2 kV ESD Tolerance, Machine Model 200V Operating Ranges (Note 2) V CC1 +60V to +85V V BOOST V CC1 to +125V V BB 7.0V to +9V V IN 0.8V to +3.5V V REF +1.6V to +1.9V V BLANK Input Voltage, VBLANK 0V to 5.5V V OUT +15V to +78V V CLAMP +55V to +118V Case Temperature −20˚C to 100˚C AC Driver Electrical Characteristics (See Figure 4 for Test Circuit) Unless otherwise noted: V CC = +80V, VBB = +8V, VIN = 2.500 VDC,CL = 8 pF, Output = 40 VPP at 1 MHz, TC = 50˚C, V REF = 1.735V, HEATSINK MUST BE GROUNDED. Symbol Parameter Conditions Min Typ Max Units I CC V CC Supply Current All 3 Channels, No Output Load 35 45 mA I BB V BB Supply Current All 3 Channels, No Output Load 22 35 mA I OUTTYP Typical DC Output Voltage No AC Input Signal, V IN = 2.100 VDC 62 66 70 V DC A VTYP Typical DC Voltage Gain No AC Input Signal −52 V/V I RTYP Typical Rise Time 10% to 90%, (Note 5) 6.0 ns +OS Overshoot on Rising Edge 5 % t FTYP Typical Fall Time 90% to 10%, (Note 5) 6.0 ns −OS Overshoot on Falling Edge 6 % LE Linearity Error V IN 2.0 VDC to 3.0 VDC, (Note 4) 6 % Note 1: Limits of “Absolute Maximum Ratings” indicate limits below which damage to the device will not occur. Note 2: Limits of “Operating Ratings” indicate required boundaries of conditions for which the device is functional, but is not guaranteed to meet specific performance limits. Note 3: All voltages are measured with respect to GND, unless otherwise specified. Note 4: Linearity error is the variation in DC gain from VIN = 2.0 to 3.0. Note 5: Input from signal generator: tr,tf < 1 ns. DRIVER Test Circuit Figure 4 shows the test circuit for the LM2453. This circuit allows testing of the LM2453 in a 50 Ω environment as well as with a FET probe. The 4950 Ω resistor at the output forms a 200:1 voltage divider when connected to a 50Ω load. C COMP must be ad- justed for equivalent performance to the FET probe. Performance will be affected slightly by the 5k load. DS101302-4 FIGURE 4. Test Circuit (One Channel) www.national.com 3 |
Nº de peça semelhante - LM2453 |
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Descrição semelhante - LM2453 |
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