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SI3015-BS Folha de dados(PDF) 10 Page - List of Unclassifed Manufacturers |
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SI3015-BS Folha de dados(HTML) 10 Page - List of Unclassifed Manufacturers |
10 / 54 page Si 30 35 10 Rev. 1.2 Figure 5. Serial Interface Timing Diagram (DCE = 1, FSD = 1) Table 10. Switching Characteristics—Serial Interface (DCE = 1, FSD = 1) (VA = Charge Pump, VD = 3.0 to 5.25 V, TA = 0 to 70°C for K-Grade, CL = 20 pF) Parameter1,2 Symbol Min Typ Max Unit Cycle Time, SCLK tc 354 1/256 Fs — ns SCLK Duty Cycle tdty —50 — % Delay Time, SCLK ↑ to FSYNC ↑ td1 — — 10 ns Delay Time, SCLK ↑ to FSYNC ↓ td2 — — 10 ns Delay Time, SCLK ↑ to SDO valid td3 0.25tc – 20 — 0.25tc + 20 ns Delay Time, SCLK ↑ to SDO Hi-Z td4 — — 20 ns Delay Time, SCLK ↑ to RGDT ↓ td5 — — 20 ns Setup Time, SDO Before SCLK ↓ tsu 25 — — ns Hold Time, SDO After SCLK ↓ th 20 — — ns Setup Time, SDI Before SCLK tsu2 25 — — ns Hold Time, SDI After SCLK th2 20 — — ns Notes: 1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V. 2. Refer to the section "Multiple Device Support" on page 25 for functional details. D15 D1 D0 SCLK FSYNC (m ode 1) SDO (m aster) FSD SDI t c SDO (slave 1) t d1 D14 t d2 t d3 D15 D14 D13 D0 t su t h t d4 t d3 D15 t d5 t h2 t su2 |
Nº de peça semelhante - SI3015-BS |
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Descrição semelhante - SI3015-BS |
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