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6 / 22 page 6/18 BU2505FV BU2506FV TSZ02201-0RLR0GZ10140-1-2 © 2015 ROHM Co., Ltd. All rights reserved. 11.Dec.2015 Rev.001 www.rohm.co.jp TSZ22111・15・001 Cascade Connection A data output terminal for cascade connection (DO) is available for reducing the number of ports of a CPU if more channels are needed. The DO terminal can be connected to a data input terminal (DI) of another IC. However, DO signal transitions (of the IC #1 in the figure below) are triggered by the rising edge of the CLK signal. Also, DI signal transitions of another IC (#2) should follow the restriction of the data hold time. Therefore, some amount of the delay time is needed from DO of the IC #1 to DI of the IC #2. The delay time can be made with a circuit with a resister and a capacitor. Also in some cases, a CLK signal frequency has to be decreased to ensure a margin of the data setup time. If extra CPU ports are available, it is recommended to connect independent LD signals to each IC. In this case, more ports of the CPU are needed for the LD signals, but the restrictions described above in the explanation of the cascade connection don’t have to be considered. BU2505FV BU2506FV DO LD CLK DI (#2) BU2505FV BU2506FV DO LD CLK DI (#1) CPU LD CLK DI BU2505FV BU2506FV (#2) BU2505FV BU2506FV (#1) LD CLK DI LD CLK DI LD1 LD2 DI CLK Data of #2 CLK DI(#1) LD DI(#2) Data of #2 Data of #1 DO Data of #2 delay |
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