ADC10040CIMTX datasheet(7/19 Pages) NSC

Nome de Peças	ADC10040CIMTX

Descrição Electrónicos	10-Bit, 40 MSPS, 3V, 55.5 mW A/D Converter

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Fabricante Electrônico	NSC [National Semiconductor (TI)]

Página de início	http://www.national.com

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AC Electrical Characteristics

Unless otherwise specified, the following specifications apply for V

SSA =VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN =

2V

P-P (full scale), STBY = 0V, VREF = 1.20V, (Externally Supplied), fCLK = 40 MHz, 50% Duty Cycle, CL = 10 pF/pin. Boldface

limits apply for T

A =TMIN to TMAX: all other limits TA = 25˚C

Symbol

Parameter

Conditions

Min

(Note 11)

Typ

(Note

11)

Max

(Note

11)

Units

CLK, DF, STBY, SENSE

f

CLK1

Maximum Clock Frequency

40

MHz (min)

f

CLK2

Minimum Clock Frequency

20

MHz

t

CH

Clock High Time

12.5

ns

t

CL

Clock Low Time

12.5

ns

t

CONV

Conversion Latency

6

Cycles

t

OD

Data Output Delay after a Rising

Clock Edge

T = 25˚C

2

3.3

5

ns

16

ns

t

AD

Aperture Delay

1

ns

t

AJ

Aperture Jitter

2

ps (RMS)

Over Range Recovery Time

Differential V

IN step from

±3V to 0V to get

accurate conversion

1

Clock Cycle

t

STBY

Standby Mode Exit Cycle

20

Cycles

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

Note 2: All voltages are measured with respect to GND = VSSA =VSSIO = 0V, unless otherwise specified.

Note 3: When the voltage at any pin exceeds the power supplies (VIN < VSSA or VIN > VDDA,VDDIO or VDR), the current at that pin should be limited to 25 mA.

The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.

Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the

junction-to-ambient thermal resistance (

θJA), and the ambient temperature (TA), and can be calculated using the formula PDMAX=(TJmax − TA)/θJA. In the 28-pin

TSSOP,

θJA is 96˚C/W, so PDMAX = 1,302 mW at 25˚C and 677 mW at the maximum operating ambient temperature of 85˚C. Note that the power dissipation of

this device under normal operation will typically be about 55.5 mW. The values for maximum power dissipation listed above will be reached only when the ADC10040

is operated in a severe fault condition.

Note 5: Human body model is 100 pF capacitor discharged through a 1.5 k

Ω resistor. Machine model is 220 pF discharged through 0Ω.

Note 6: The 235˚C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR) the following conditions apply: Maintain the temperature at the top

of the package body above 183˚C for a minimum of 60 seconds. The temperature measured on the package body must not exceed 220˚C. Only one excursion above

183˚C is allowed per reflow cycle. The analog inputs are protected as shown below. Input voltage magnitude up to 500 mV beyond the supply rails will not damage

this device. However, input errors will be generated if the input goes above VDDA or VDDIO and below VSSA or VSSIO.

20077807

Note 7: To guarantee accuracy, it is required that |VDDA–VDDIO| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

Note 8: With the test condition for 2 VP-P differential input, the 10-bit LSB is 1.95 mV.

Note 9: Typical figures are at TA =TJ = 25˚C and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality

Level).

Note 10: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative

full-scale.

Note 11: Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge, and VIH = 2.4V for a rising edge.

Note 12: Optimum dynamic performance will be obtained by keeping the reference input in the +1.2V.

Note 13: VDDIO is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply

voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR =VDR x(C0 xf0 +C1 xf1 +C2 +f2 +....C11 xf11) where VDR is the

output driver supply voltage, Cn is the total load capacitance on the output pin, and fn is the average frequency at which the pin is toggling.

Note 14: Power consumption includes output driver power. (fIN = 0 MHz).

Note 15: The input bandwidth is limited using a 10 pF capacitor between VIN− and VIN+.

Note 16: VCOM is a typical value, measured at room temperture. It is not guaranteed by test.

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