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LM2653 Folha de dados(PDF) 9 Page - National Semiconductor (TI) |
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LM2653 Folha de dados(HTML) 9 Page - National Semiconductor (TI) |
9 / 13 page Operation (Continued) LAY CAPACITOR section for more information.) Toggling the input supply voltage or the shutdown pin can reset the device from the latched protection mode. PGOOD Flag The PGOOD flag goes low whenever the overvoltage or undervoltage latch protection is enabled. DESIGN PROCEDURE This section presents guidelines for selecting external com- ponents. INPUT CAPACITOR A low ESR aluminum, tantalum, or ceramic capacitor is needed betwen the input pin and power ground. This capaci- tor prevents large voltage transients from appearing at the input. The capacitor is selected based on the RMS current and voltage requirements. The RMS current is given by: The RMS current reaches its maximum (I OUT/2) when V IN equals 2VOUT. For an aluminum or ceramic capacitor, the voltage rating should be at least 25% higher than the maximum input voltage. If a tantalum capacitor is used, the voltage rating required is about twice the maximum input voltage. The tantalum capacitor should be surge current tested by the manufacturer to prevent shorted by the inrush current. It is also recommended to put a small ceramic capacitor (0.1 µF) between the input pin and ground pin to reduce high frequency spikes. INDUCTOR The most critical parameters for the inductor are the induc- tance, peak current and the DC resistance. The inductance is related to the peak-to-peak inductor ripple current, the input and the output voltages: A higher value of ripple current reduces inductance, but increases the conductance loss, core loss, current stress for the inductor and switch devices. It also requires a bigger output capacitor for the same output voltage ripple require- ment. A reasonable value is setting the ripple current to be 30% of the DC output current. Since the ripple current in- creases with the input voltage, the maximum input voltage is always used to determine the inductance. The DC resistance of the inductor is a key parameter for the efficiency. Lower DC resistance is available with a bigger winding area. A good tradeoff between the efficiency and the core size is letting the inductor copper loss equal 2% of the output power. OUTPUT CAPACITOR The selection of C OUT is driven by the maximum allowable output voltage ripple. The output ripple in the constant fre- quency, PWM mode is approximated by: The ESR term usually plays the dominant role in determining the voltage ripple. A low ESR aluminum electrolytic or tanta- lum capacitor (such as Nichicon PL series, Sanyo OS-CON, Sprague 593D, 594D, AVX TPS, and CDE polymer alumi- num) is recommended. An electrolytic capacitor is not rec- ommended for temperatures below −25˚C since its ESR rises dramatically at cold temperature. A tantalum capacitor has a much better ESR specification at cold temperature and is preferred for low temperature applications. The output voltage ripple in constant frequency mode has to be less than the sleep mode voltage hysteresis to avoid entering the sleep mode at full load: V RIPPLE < 20mV * VOUT /VFB BOOST CAPACITOR A 0.1 µF ceramic capacitor is recommended for the boost capacitor. The typical voltage across the boost capacitor is 6.7V. SOFT-START CAPACITOR A soft-start capacitor is used to provide the soft-start feature. When the input voltage is first applied, or when the SD(SS) pin is allowed to go high, the soft-start capacitor is charged by a current source (approximately 2 µA). When the SD(SS) pin voltage reaches 0.6V (shutdown threshold), the internal regulator circuitry starts to operate. The current charging the soft-start capacitor increases from 2 µA to approximately 10 µA. With the SD(SS) pin voltage between 0.6V and 1.3V, the level of the current limit is zero, which means the output voltage is still zero. When the SD(SS) pin voltage increases beyond 1.3V, the current limit starts to increase. The switch duty cycle, which is controlled by the level of the current limit, starts with narrow pulses and gradually gets wider. At the same time, the output voltage of the converter increases towards the nominal value, which brings down the output voltage of the error amplifier. When the output of the error amplifier is less than the current limit voltage, it takes over the control of the duty cycle. The converter enters the normal current-mode PWM operation. The SD(SS) pin voltage is eventually charged up to about 2V. The soft-start time can be estimated as: T SS =CSS * 0.6V/2 µA + CSS * (2V−0.6V)/10 µA During start-up, the internal circuit is monitoring the soft-start voltage. When the softstart voltage reaches 2V, the under- voltage and overvoltage protections are enabled. If the output voltage doesn’t rise above 80% of the normal value before the soft-start reaches 2V. The undervoltage protection will kick in and shut the device down. You can avoid this by either increasing the value of the soft-start capacitor, or using a LDELAY capacitor. LDELAY CAPACITOR As mentioned in the operation section, the LDELAY capaci- tor sets the time delay between the output voltage goes below 80% of its nominal value and the undervoltage latch protection is enabled. Charging the CDELAY bya5µA current source up to 2V sets the delay time. Therefore, T DELAY =CDELAY * 2V/5µA. www.national.com 9 |
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