STK14C88

December 2002

3

Document Control # ML0014 rev 0.0

SRAM READ CYCLES #1 & #2

Note g: W and HSB must be high during SRAM READ cycles and low during SRAM WRITE cycles.

Note i:

Measured

± 200mV from steady state output voltage.

SRAM READ CYCLE #1: Address Controlledg, h

SRAM READ CYCLE #2: E Controlledg

NO.

SYMBOLS

PARAMETER

STK14C88-25

STK14C88-35

STK14C88-45

UNITS

#1, #2

Alt.

MIN

MAX

MIN

MAX

MIN

MAX

Chip Enable Access Time

25

35

45

ns

Read Cycle Time

25

35

45

ns

Address Access Time

25

35

45

ns

Output Enable to Data Valid

10

15

20

ns

Output Hold after Address Change

5

5

5

ns

Chip Enable to Output Active

5

5

5

ns

Chip Disable to Output Inactive

10

13

15

ns

Output Enable to Output Active

0

0

0

ns

Output Disable to Output Inactive

10

13

15

ns

10

Chip Enable to Power Active

0

0

0

ns

11

Chip Disable to Power Standby

25

35

45

ns

DATA VALID

5

3

DQ (DATA OUT)

ADDRESS

2

6

STANDBY

DATA VALID

4

DQ (DATA OUT)

E

ADDRESS

2

G

ACTIVE

10

11

7

8

1

9