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BD37513FS Folha de dados(PDF) 9 Page - Rohm

Nome de Peças BD37513FS
Descrição Electrónicos  Sound Processor with Built-in 2-band Equalizer
Download  30 Pages
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Fabricante Electrônico  ROHM [Rohm]
Página de início  http://www.rohm.com
Logo ROHM - Rohm

BD37513FS Folha de dados(HTML) 9 Page - Rohm

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BD37513FS
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TSZ02201-0C2C0E100430-1-2
© 2015 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
16.Dec.2015 Rev.001
Timing Chart
Control Signal Specification
(1) Electrical Specifications and Timing for bus Lines and I/O Stage
Figure 13. I2C-bus Signal Timing Diagram
Table 1 Characteristics of the SDA and SCL bus lines for I2C-bus devices
Parameter
Symbol
Fast-mode I2C-bus
Unit
Min
Max
1
SCL clock frequency
fSCL
0
400
kHz
2
Bus free time between a STOP and START condition
tBUF
1.3
μS
3
Hold time (repeated) START condition. After this period, the first clock
pulse is generated
tHD;STA
0.6
μS
4
LOW period of the SCL clock
tLOW
1.3
μS
5
HIGH period of the SCL clock
tHIGH
0.6
μS
6
Set-up time for a repeated START condition
tSU;STA
0.6
μS
7
Data hold time:
tHD;DAT
0.06(Note)
μS
8
Data set-up time
tSU;DAT
120
ns
9
Set-up time for STOP condition
tSU;STO
0.6
μS
All values referred to VIH Min and VIL Max Levels (see Table 2).
(Note) To avoid sending right after the fall-edge of SCL (VIH min of the SCL signal), the transmitting device should set a hold time of 300ns or more for the SDA
signal.
For 7(tHD;DAT), 8(tSU;DAT), make the setup in which the margin is fully in.
Table 2 Characteristics of the SDA and SCL I/O stages for I2C-bus devices
Parameter
Symbol
Fast-mode devices
Unit
Min
Max
10
LOW level input voltage:
VIL
-0.3
+1
V
11
HIGH level input voltage:
VIH
2.3
5
V
12
Pulse width of spikes which must be suppressed by the input filter.
tSP
0
50
ns
13
LOW level output voltage: at 3mA sink current
VOL1
0
0.4
V
14
Input current of each I/O pin with an input voltage between 0.4V and
4.5V.
II
-10
+10
μA
SDA
S
SCL
tLOW
tR
tHD;DAT
P
tHD;STA
tHIGH
tBUF
tF
tSU;DAT
tSU;STAT
tSU;STOT
tSP
tHD;STAT
Sr
P
Figure 14. I2C Data Transmission Command Timing Diagram
tBUF
:4us
tHD;STA
:2us
tHD;DAT
:1us
tLOW
:3us
tHIGH
:1us
tSU;DAT
:1us
tSU;STO
:2us
SCL clock frequency:250kHz
SCL
SDA
tHD;STA
:2µs
tHD;DAT
:1µs
tSU;DAT
:1µs
tSU;STO
:2µs
tLOW
:3µs
tHIGH
:1µs
tBUF
:4µs
SDA
SCL
SCL clock frequency : 250kHz


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