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TP5510N Folha de dados(PDF) 3 Page - National Semiconductor (TI) |
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TP5510N Folha de dados(HTML) 3 Page - National Semiconductor (TI) |
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3 / 12 page  Pin Description (Continued) Symbol Function MCLKD PDN Encode master clock Must be 1536 MHz 1544 MHz or 2048 MHz May be asyn- chronous with MCLKE but should be syn- chronous with MCLKE for best perform- ance When MCLKD is connected continu- ously low MCLKE is selected for all inter- nal timing When MCLKD is connected continuously high the device is powered down MCLKE Encode master clock Must be 1536 MHz 1544 MHz or 2048 MHz May be asyn- chronous with MCLKD Best performance is realized from synchronous operation FSE Encode frame sync pulse input which en- ables BCLKE to shift out the data on DE FSE is an 8 kHz pulse train see Figures 2 and 3 for timing details BCLKE The bit clock which shifts out the data on DE May vary from 64 kHz to 2048 MHz but must be synchronous with MCLKE DE The TRI-STATE data output which is en- abled by FSE TSE Open drain output which pulses low during the AD time slot GSE Analog output of the encode input amplifi- er Used to externally set gain VFEIb Inverting input of the encode input amplifi- er VFEIa Non-inverting input of the encode input amplifier Functional Description POWER-UP When power is first applied power-on reset circuitry initializ- es the AFE and places it into a power-down state All non- essential circuits are deactivated and the DE and VFDO out- puts are put in high impedance states To power-up the de- vice a logical low level or clock must be applied to the MCLKD PDN pin and FSE andor FSD pulses must be pres- ent Thus 2 power-down control modes are available The first is to pull the MCLKD PDN pin high the alternative is to hold both FSE and FSD inputs continuously lowthe device will power-down approximately 2 ms after the last FSE or FSD pulse Power-up will occur on the first FSE or FSD pulse The TRI-STATE data output DE will remain in the high impedance state until the second FSE pulse SYNCHRONOUS OPERATION For synchronous operation the same master clock and bit clock should be used for both the encode and decode direc- tions In this mode a clock must be applied to MCLKE and the MCLKD PDN pin can be used as a power-down control A low level on MCLKD PDN powers up the device and a high level powers down the device In either case MCLKE will be selected as the master clock for both the encode and decode circuits A bit clock must also be applied to BCLKE and the BCLKD CLKSEL can be used to select the proper internal divider for a master clock of 1536 MHz 1544 MHz or 2048 MHz For 1544 MHz operation the device auto- matically compensates for the 193rd clock pulse each frame With a fixed level on the BCLKD CLKSEL pin BCLKE will be selected as the bit clock for both the encode and decode directions Table 1 indicates the frequencies of operation which can be selected depending on the state of BCLKD CLKSEL In this synchronous mode the bit clock BCLKE may be from 64 kHz to 2048 MHz but must be synchro- nous with MCLKE Each FSE pulse begins the encoding cycle and the data from the previous encode cycle is shifted out of the enabled DE output on the positive edge of BCLKE After 8-bit clock periods the TRI-STATE DE output is returned to a high im- pedance state With an FSD pulse data is latched via the DD input on the negative edge of BCLKE (or BCLKD if run- ning) FSE and FSD must be synchronous with MCLKED TABLE I Selection of Master Clock Frequencies BCLKD CLKSEL Master Clock Frequency Selected TP5510 Clocked 1536 MHz or 1544 MHz 0 2048 MHz 1 1536 MHz or 1544 MHz ASYNCHRONOUS OPERATION For asynchronous operation separate encode and decode clocks may be applied MCLKE and MCLKD must be 1536 MHz or 1544 MHz for the TP5510 and need not be synchronous For best transmission performance however MCLKD should be synchronous with MCLKE which is easily achieved by applying only static logic levels to the MCLKD PDN pin This will automatically connect MCLKE to all inter- nal MCLKD functions (see Pin Description) For 1544 MHz operation the device automatically compensates for the 193rd clock pulse each frame FSE starts each AD conver- sion cycle and must be synchronous with MCLKE and BCLKE FSD starts each DA conversion cycle and must be synchronous with BCLKD BCLKD must be a clock the logic levels shown in Table 1 are not valid in asynchronous mode BCLKE and BCLKD may operate from 64 kHz to 2048 MHz SHORT FRAME SYNC OPERATION The AFE can utilize either a short frame sync pulse or a long frame sync pulse Upon power initialization the device as- sumes a short frame mode In this mode both frame sync pulses FSE and FSD must be one bit clock period long with timing relationships specified in Figure 2 With FSE high during a falling edge of BCLKE the next rising edge of BCLKE enables the DE TRI-STATE output buffer which will output the sign bit The following seven rising edges clock out the remaining seven bits and the next falling edge dis- ables the DE output With FSD high during a falling edge of BCLKD (BCLKE in synchronous mode) the next falling edge of BCLKE latches in the sign bit The following seven falling http www nationalcom 3 |
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Descrição semelhante - TP5510N |
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