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74LVC1G18GV Folha de dados(PDF) 2 Page - NXP Semiconductors |
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74LVC1G18GV Folha de dados(HTML) 2 Page - NXP Semiconductors |
2 / 14 page 2003 Jul 25 2 Philips Semiconductors Product specification 1-of-2 non-inverting demultiplexer with 3-state deselected output 74LVC1G18 FEATURES • Wide supply voltage range from 1.65 to 5.5 V • 5 V tolerant input/output for interfacing with 5 V logic • High noise immunity • Complies with JEDEC standard: – JESD8-7 (1.65 to 1.95 V) – JESD8-5 (2.3 to 2.7 V) – JESD8B/JESD36 (2.7 to 3.6 V). • ESD protection: – HBM EIA/JESD22-A114-A exceeds 2000 V – MM EIA/JESD22-A115-A exceeds 200 V. •±24 mA output drive (VCC = 3.0 V) • CMOS low power consumption • Latch-up performance exceeds 250 mA • Direct interface with TTL levels • SOT363 and SOT457 package • Specified from −40 to +85 °C and −40 to +125 °C. DESCRIPTION The 74LVC1G18 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Input can be driven from either 3.3 or 5 V devices. These features allow the use of these devices in a mixed 3.3 and 5 V environment. This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74LVC1G18 is a 1-of-2 non-inverting demultiplexer with a 3-state output. The 74LVC1G18 buffers the data on input pin A and passes it either to output 1Y or 2Y, depending on whether the state of the select input (pin S) is LOW or HIGH. QUICK REFERENCE DATA GND = 0 V; Tamb =25 °C. Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi × N+ ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; ∑ (CL × VCC2 × fo) = sum of outputs. 2. The condition is VI = GND to VCC. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH propagation delay input A to output nY VCC = 1.8 V; CL = 30 pF; RL =1kΩ 5.1 ns VCC = 2.5 V; CL = 30 pF; RL = 500 Ω 3.2 ns VCC = 2.7 V; CL = 50 pF; RL = 500 Ω 3.2 ns VCC = 3.3 V; CL = 50 pF; RL = 500 Ω 3.0 ns VCC = 5.0 V; CL = 50 pF; RL = 500 Ω 2.3 ns CI input capacitance 2.5 pF CPD power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2 28.8 pF |
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