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AD1812 Folha de dados(PDF) 5 Page - Analog Devices

Nome de Peças AD1812
Descrição Electrónicos  SoundPort Controller
Download  20 Pages
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

AD1812 Folha de dados(HTML) 5 Page - Analog Devices

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AD1812
REV. 0
–5–
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter
Symbol
Min
Typ
Max
Units
IOW
/IOR Strobe Width
tSTW
100
ns
IOW
/IOR Rising to IOW/IOR Falling
tBWDN
80
ns
Write Data Setup to IOW Rising
tWDSU
10
ns
IOR
Falling to Valid Read Data
tRDDV
40
ns
AEN Setup to IOW/IOR Falling
tAESU
10
ns
AEN Hold from IOW/IOR Rising
tAEHD
0ns
Adr Setup to IOW/IOR Falling
tADSU
10
ns
Adr Hold from IOW/IOR Rising
tADHD
10
ns
DACK
Rising to IOW/IOR Falling
tDKSU1
20
ns
IOW
/IOR Rising to DACK Falling
tDKHD1
0ns
DACK
Setup to IOW/IOR Falling
tDKSU2
10
ns
Data Hold from IOR Rising
tDHD1
20
ns
Data Hold from IOW Rising
tDHD2
15
ns
DRQ Hold from IOW/IOR Falling
tDRHD
25
ns
DACK
Hold from IOW Rising
tDKHD2
10
ns
DACK
Hold from IOR Rising
tDKHD3
10
ns
*Guaranteed, not tested.
Specifications subject to change without notice.
General Notes
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield
meaningful results for an additional device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, you cannot meaningfully add
up parameters to derive longer times. Note that all 8-bit DMA transfers occur on channels 0, 1, and 3, while all 16-bit DMA transfers occur on channels 5, 6, and 7.
tDKSU1
tDKHD1
tAESU
tAEHD
tSTW
tRDDV
tDHD1
tADHD
tADSU
DRQ
(0, 1, 3, 5, 6, 7)
DACK
(0, 1, 3, 5, 6, 7)
AEN
IOR
PC_D (7:0) /
PC_D (15:0)
PC_A (15:0)
Figure 1. PIO Read Cycle
tDKHD3
tAESU
tAEHD
tRDDV
tDHD1
tDKSU2
tDRHD
DRQ
(0, 1, 3, 5, 6, 7)
DACK
(0, 1, 3, 5, 6, 7)
AEN
IOR
PC_D (7:0) /
PC_D (15:0)
tSTW
Figure 3. DMA Read Cycle
tDKSU1
tDKHD1
tAESU
tAEHD
tSTW
tDHD2
tADHD
DRQ
(0, 1, 3, 5, 6, 7)
DACK
(0, 1, 3, 5, 6, 7)
AEN
IOW
PC_D (7:0) /
PC_D (15:0)
PC_A (15:0)
tADSU
tWDSU
Figure 2. PIO Write Cycle
tDKHD2
tAESU
tAEHD
tDHD2
tDKSU2
tDRHD
DRQ
(0, 1, 3, 5, 6, 7)
DACK
(0, 1, 3, 5, 6, 7)
AEN
IOW
PC_D (7:0) /
PC_D (15:0)
tSTW
tWDSU
Figure 4. DMA Write Cycle


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