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ADF4360-5BCP Folha de dados(PDF) 7 Page - Analog Devices |
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ADF4360-5BCP Folha de dados(HTML) 7 Page - Analog Devices |
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7 / 20 page  PRELIMINARY TECHNICAL DATA ADF4360-2 REV. PrA 07/03 –7– Figure 2. Reference Input Stage A AND B COUNTERS The A and B CMOS counters combine with the dual modulus prescaler to allow a wide ranging division ratio in the PLL feedback counter. The counters are specified to work when the prescaler output is 300MHz or less. Thus, with an VCO frequency of 2.5GHz, a prescaler value of 16/17 is valid but a value of 8/9 is not valid. Pulse Swallow Function The A and B counters, in conjunction with the dual modulus prescaler make it possible to generate output frequencies which are spaced only by the Reference Frequency divided by R . The equation for the VCO frequency is as follows: fVCO = [(P x B) + A] x fREFIN/R fVCO Ouput Frequency of voltage controlled oscillator (VCO). P Preset modulus of dual modulus prescaler (8/9, 16/17, etc.,). B Preset Divide Ratio of binary 13-bit counter (3 to 8191). A Preset Divide Ratio of binary 5-bit swallow counter (0 to 31). fREFIN External reference frequency oscillator. Powerdown Control 100k Ω NC To R Counter REFIN Buffer NC NO SW1 SW2 SW3 CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The Reference Input stage is shown below in Figure 2. SW1 and SW2 are normally-closed switches. SW3 is normally- open. When Powerdown is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on powerdown. PRESCALER (P/P+1) The dual modulus prescaler (P/P+1), along with the A and B counters, enables the large division ratio, N, to be realised (N = BP + A). The dual-modulus prescaler, operating at CML levels, takes the clock from the VCO and divides it down to a manageable frequency for the CMOS A and B counters. The prescaler is programmable. It can be set in software to 8/9, 16/17 or 32/33. It is based on a synchronous 4/5 core. There is a minimum divide ratio possible for fully contiguous output frequencies. This minimum is determined by P, the prescaler value and is given by: (P 2-P). Figure 3. A and B Counters PRESCALER P/P+1 13-BIT B COUNTER 5-BIT A COUNTER LOAD LOAD N = BP + A From VCO To PFD Modulus Control N DIVIDER |
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Descrição semelhante - ADF4360-5BCP |
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