1

V

DD

8

GND

2

V

REF

7

D

IN

3

V

FB

6

SCLK

4

V

OUT

5

SYNC

4

DAC8551-Q1, DAC6551-Q1

SLASEB8C – FEBRUARY 2016 – REVISED NOVEMBER 2016

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Product Folder Links: DAC8551-Q1 DAC6551-Q1

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Copyright © 2016, Texas Instruments Incorporated

5 Pin Configuration and Functions

DGK Package

8-Pin VSSOP

Top View

Pin Functions

PIN

TYPE

DESCRIPTION

NAME

NO.

7

I

Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock

input. Schmitt-trigger logic input.

GND

8

GND

Ground reference point for all circuitry on the device

SCLK

6

I

Serial clock input. Data can be transferred at rates up to 30 MHz. Schmitt-trigger logic input.

SYNC

5

I

Level-triggered control input (active-low). This is the frame synchronization signal for the input data. SYNC

going low enables the input shift register, and data is transferred in on the falling edges of the following

clocks. The DAC is updated following the 24th clock (unless SYNC is taken high before this edge, in which

case the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the device).

Schmitt-trigger logic input.

1

PWR

Power supply input, 3 V to 5.5 V

3

I

4

O

Analog output voltage from DAC. The output amplifier has rail-to-rail operation.

2

I

Reference voltage input

(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

–0.3

6

V

Digital input voltage to GND

–0.3

V

–0.3

V

–0.3

V

–0.3

V

–65

150

°C

–65

150

°C