© Semiconductor Components Industries, LLC, 2013

May, 2013 − Rev. 9

1

Publication Order Number:

MC14514B/D

MC14514B, MC14515B

4-Bit Transparent Latch /

4-to-16 Line Decoder

The MC14514B and MC14515B are two output options of a 4 to 16

line decoder with latched inputs. The MC14514B (output active high

option) presents a logical “1” at the selected output, whereas the

MC14515B (output active low option) presents a logical “0” at the

selected output. The latches are R−S type flip−flops which hold the

last input data presented prior to the strobe transition from “1” to “0”.

These high and low options of a 4−bit latch / 4 to 16 line decoder are

constructed with N−channel and P−channel enhancement mode

devices in a single monolithic structure. The latches are R−S type

flip−flops and data is admitted upon a signal incident at the strobe

input, decoded, and presented at the output.

These complementary circuits find primary use in decoding

applications where low power dissipation and/or high noise immunity

is desired.

Features

Schottky TTL Load the Rated Temperature Range

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

Parameter

Symbol

Value

Unit

DC Supply Voltage Range

−0.5 to +18.0

V

Input or Output Voltage Range

(DC or Transient)

+0.5

V

Input or Output Current (DC or Transient)

per Pin

±10

mA

Power Dissipation per Package (Note 1)

500

mW

Ambient Temperature Range

−55 to +125

°C

Storage Temperature Range

−65 to +150

°C

Lead Temperature (8−Second Soldering)

260

°C

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Temperature Derating: Plastic “P and D/DW”

Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

Unused inputs must always be tied to an appropriate logic voltage level

xx

= 14 or 15

A

= Assembly Location

WL

= Wafer Lot

YY

= Year

WW = Work Week

G

= Pb−Free Package

MARKING DIAGRAM

1

24

SOIC−24

DW SUFFIX

CASE 751E

145xxB

AWLYYWWG

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

http://onsemi.com

S5

S7

D2

D1

ST

S3

S4

S6

S10

D3

D4

INH

S15

S14

S9

5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

13

11

12

21

22

23

24

S13

S12

S8

S11

S0

S2

S1

PIN ASSIGNMENT