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FM30C256-S Folha de dados(PDF) 8 Page - List of Unclassifed Manufacturers

Nome de Peças FM30C256-S
Descrição Electrónicos  256Kb Data Collector
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Fabricante Electrônico  ETC [List of Unclassifed Manufacturers]
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FM30C256
Rev 2.1
Dec. 2002
Page 8 of 18
Tamper Detection and Time Stamp
The TIN pin is a battery-backed input that is used to
detect a tamper event in the system. When a rising
edge occurs on TIN, this Tamper Detect event is
recorded in the MSB of register 0. This action will
occur only when either VBAK or VDD is applied. Any
further activity on TIN, such as a falling edge, will be
ignored. The user is responsible for reading and
clearing the Tamper flag. Clearing the Tamper flag
allows the TIN to detect another rising edge. The
tamper flag can only be read or cleared when VDD
4.5V. On a power-up without battery, this bit is set to
zero.
The tamper input TIN can be used to timestamp the
exact time a tamper event occurs. This feature can be
enabled by setting the timestamp enable bit TSEN in
the calibration control register (RTC address 1, bit
D6). At power-up, TSEN is cleared and must be set
by the user. When a rising edge occurs on TIN and
the TSEN bit is set, the date and time of the event
will be recorded. The current time is loaded into the
timekeeping registers. When the system is checked
for a tamper event, the time of the event can be read.
After a tamper event, the timekeeping registers can
be overwritten if the R bit is set before reading the
timekeeping registers. To prevent overwriting the
timestamp, the control register should be read first to
check that the tamper bit is set. If it is set, the
timekeeping registers should be read to collect the
time of the last tamper event. Checking for a tamper
event before setting the R bit will ensure accurate
tamper timestamp information. If the TSEN bit is
not set, then a rising edge on TIN will not trigger a
timestamp.
System Reset Control
The /RST pin allows the user to easily control a
system level reset function. It is an open drain
output and requires an external pullup resistor to
VDD for proper operation. When VDD is within the
specified operating range, /RST output is tri-stated
and pulled to VDD by the external resistor. If VDD
drops below the reset trip point voltage level (VTP)
and remains below this level for the VTP noise
immunity duration (tRNR), the /RST pin will be
driven low. It will continue to drive low until VDD
falls below the VRST level. When VDD rises again
above VTP, /RST will continue to drive low for a
duration (tRPU) to ensure a robust system reset at a
reliable VDD level. After tRPU has been met, the /RST
pin tri-states and is pulled high by the external
pullup resistor. Refer to the figure on page 16 for a
graphical description of the /RST function and
timing.
9
512.0189
512.0211
36.90
41.23
001001
10
512.0211
512.0233
41.24
45.57
001010
11
512.0233
512.0256
45.58
49.91
001011
12
512.0256
512.0278
49.92
54.25
001100
13
512.0278
512.0300
54.26
58.59
001101
14
512.0300
512.0322
58.60
62.93
001110
15
512.0322
512.0344
62.94
67.27
001111
16
512.0344
512.0367
67.28
71.61
010000
17
512.0367
512.0389
71.62
75.95
010001
18
512.0389
512.0411
75.96
80.29
010010
19
512.0411
512.0433
80.30
84.63
010011
20
512.0433
512.0456
84.64
88.97
010100
21
512.0456
512.0478
88.98
93.31
010101
22
512.0478
512.0500
93.32
97.65
010110
23
512.0500
512.0522
97.66
101.99
010111
24
512.0522
512.0544
102.00
106.33
011000
25
512.0544
512.0567
106.34
110.67
011001
26
512.0567
512.0589
110.68
115.01
011010
27
512.0589
512.0611
115.02
119.35
011011
28
512.0611
512.0633
119.36
123.69
011100
29
512.0633
512.0656
123.70
128.03
011101
30
512.0656
512.0678
128.04
132.37
011110
31
512.0678
512.0700
132.38
136.71
011111


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