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MC100ELT26 Folha de dados(PDF) 1 Page - Motorola, Inc |
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MC100ELT26 Folha de dados(HTML) 1 Page - Motorola, Inc |
1 / 2 page MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3–1 REV 2 © Motorola, Inc. 1996 1/95 Product Preview 1:2 Fanout Differential PECL to TTL Translator The MC10ELT/100ELT26 is a 1:2 fanout differential PECL to TTL translator. Because PECL (Positive ECL) levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the 1:2 fanout design of the ELT23 makes it ideal for applications which require the low skew duplication of a signal in a tightly packed PC board. Because the mature MOSAIC 1.5 process is used, low cost can be added to the list of features. The VBB output allows the ELT26 to also be used in a single-ended input mode. In this mode the VBB output is tied to the IN input for a non-inverting buffer or the IN input for an inverting buffer. If used the VBB pin should be bypassed to ground via a 0.01 µF capacitor. The ELT26 is available in both ECL standards: the 10ELT is compatible with positive MECL 10H logic levels while the 100ELT is compatible with positive ECL 100K logic levels. • 3.5ns Typical Propagation Delay • <500ps Typical Output to Output Skew • Differential PECL Inputs • Small Outline SOIC Package • 24mA TTL Outputs • Flow Through Pinouts 1 2 3 4 5 6 7 8 Q0 GND VCC LOGIC DIAGRAM AND PINOUT ASSIGNMENT D Q1 D VBB NC PECL TTL This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. MC10ELT26 MC100ELT26 PIN FUNCTION Qn TTL Outputs D Diff PECL Input VCC +5.0V Supply VBB Reference Output GND Ground PIN DESCRIPTION 1 8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751-05 |
Nº de peça semelhante - MC100ELT26 |
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Descrição semelhante - MC100ELT26 |
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