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AD4003BRMZ Folha de dados(PDF) 6 Page - Analog Devices

Nome de Peças AD4003BRMZ
Descrição Electrónicos  18-Bit, 2 MSPS Precision SAR Differential ADC
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

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Data Sheet
AD4003
Rev. 0 | Page 5 of 33
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
VIO Only
2 MSPS, high-Z mode disabled
1.0
mW
Energy per Conversion
8
nJ/sample
TEMPERATURE RANGE
Specified Performance
TMIN to TMAX
−40
+125
°C
1
The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS.
2
A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 75 MHz. Refer to Table 4 for the maximum achievable
throughput for different modes of operation.
3
Transient response is the time required for the ADC to acquire a full-scale input step to ±1 LSB accuracy.
4
The minimum and maximum values are guaranteed by characterization, not production tested.
5
See the 1/f noise plot in Figure 18.
TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V; VIO = 1.71 V to 5.5 V; VREF = 5 V; all specifications TMIN to TMAX, high-Z mode disabled, span compression
disabled, and turbo mode enabled (fS = 2 MSPS), unless otherwise noted.1
Table 2. Digital Interface Timing
Parameter
Symbol
Min
Typ
Max
Unit
Conversion Time—CNV Rising Edge to Data Available
tCONV
290
320
ns
Acquisition Phase2
tACQ
290
ns
Time Between Conversions
tCYC
500
ns
CNV Pulse Width (CS Mode)3
tCNVH
10
ns
SCK Period (CS Mode)4
tSCK
VIO > 2.7 V
9.8
ns
VIO > 1.7 V
12.3
ns
SCK Period (Daisy-Chain Mode)5
tSCK
VIO >2.7 V
20
ns
VIO > 1.7 V
25
ns
SCK Low Time
tSCKL
3
ns
SCK High Time
tSCKH
3
ns
SCK Falling Edge to Data Remains Valid Delay
tHSDO
1.5
ns
SCK Falling Edge to Data Valid Delay
tDSDO
VIO >2.7 V
7.5
ns
VIO >1.7 V
10.5
ns
CNV or SDI Low to SDO D17 MSB Valid Delay (CS Mode)
tEN
VIO >2.7 V
10
ns
VIO >1.7 V
13
ns
CNV Rising Edge to First SCK Rising Edge Delay
tQUIET1
190
ns
Last SCK Falling Edge to CNV Rising Edge Delay6
tQUIET2
60
ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
tDIS
20
ns
SDI Valid Setup Time from CNV Rising Edge
tSSDICNV
2
ns
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
tHSDICNV
2
ns
SCK Valid Hold Time from CNV Rising Edge (Daisy-Chain Mode)
tHSCKCNV
12
ns
SDI Valid Setup Time from SCK Rising Edge (Daisy-Chain Mode)
tSSDISCK
2
ns
SDI Valid Hold Time from SCK Rising Edge (Daisy-Chain Mode)
tHSDISCK
2
ns
1
See Figure 2 for the timing voltage levels.
2
The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS.
3
For turbo mode, tCNVH must match the tQUIET1 minimum.
4
A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 75 MHz.
5
A 50% duty cycle is assumed for SCK.
6
See Figure 22 for SINAD vs. tQUIET2.


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