SI4420 datasheet(3/33 Pages) SILABS

Nome de Peças	SI4420

Descrição Electrónicos	No alignment required in production

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Fabricante Electrônico	SILABS [Silicon Laboratories]

Página de início	http://www.silabs.com

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Si4420

3

Data Validity Blocks

RSSI

A digital RSSI output is provided to monitor the input signal level.

It goes high if the received signal strength exceeds a given

preprogrammed level. An analog RSSI signal is also available.

The RSSI settling time depends on the external filter capacitor.

Pin 15 is used as analog RSSI output. The digital RSSI can be

can be monitored by reading the status register.

Analog RSSI Voltage vs. RF Input Power

Input Power [dBm]

RSSI

voltage

[V]

P4

P2

P1

P3

P1

-65 dBm

1300 mV

P2

-65 dBm

1000 mV

P3

-100 dBm

600 mV

P4

-100 dBm

300 mV

DQD

The Data Quality Detector is based on counting the spikes on the

unfiltered received data. For correct operation, the “DQD

threshold” parameter must be filled in by using the Data Filter

Command.

AFC

By using an integrated Automatic Frequency Control (AFC)

feature, the receiver can minimize the TX/RX offset in discrete

steps, allowing the use of:

 Inexpensive, low accuracy crystals

 Narrower receiver bandwidth (i.e. increased sensitivity)

 Higher data rate

Crystal Oscillator

The Si4420 has a single-pin crystal oscillator circuit, which

provides a 10 MHz reference signal for the PLL. To reduce

external parts and simplify design, the crystal load capacitor is

internal and programmable. Guidelines for selecting the

appropriate crystal can be found later in this datasheet.

The transceiver can supply the clock signal for the

microcontroller; so accurate timing is possible without the need

for a second crystal.

When the microcontroller turns the crystal oscillator off by

clearing the appropriate bit using the Configuration Setting

Command, the chip provides a fixed number (196) of further

clock pulses (“clock tail”) for the microcontroller to let it go to idle

or sleep mode.

Low Battery Voltage Detector

The low battery detector circuit monitors the supply voltage and

generates an interrupt if it falls below a programmable threshold

level. The detector circuit has 50 mV hysteresis.

Wake-Up Timer

The wake-up timer has very low current consumption (1.5 μA

typical) and can be programmed from 1 ms to several days with

an accuracy of ±5%.

It calibrates itself to the crystal oscillator at every startup. When

the crystal oscillator is switched off, the calibration circuit

switches it on only long enough for a quick calibration (a few

milliseconds) to facilitate accurate wake-up timing.

Event Handling

In order to minimize current consumption, the transceiver

supports different power saving modes. Active mode can be

initiated by several wake-up events (negative logical pulse on

nINT input, wake-up timer timeout, low supply voltage detection,

on-chip FIFO filled up or receiving a request through the serial

interface).

If any wake-up event occurs, the wake-up logic generates an

interrupt signal, which can be used to wake up the

microcontroller,

effectively

reducing

the

period

the

microcontroller has to be active. The source of the interrupt can

be read out from the transceiver by the microcontroller through

the SDO pin.

Interface and Controller

An SPI compatible serial interface lets the user select the

frequency band, center frequency of the synthesizer, and the

bandwidth of the baseband signal path. Division ratio for the

microcontroller clock, wake-up timer period, and low supply

voltage detector threshold are also programmable. Any of these

auxiliary functions can be disabled when not needed. All

parameters are set to default after power-on; the programmed

values are retained during sleep mode. The interface supports

the read-out of a status register, providing detailed information

about the status of the transceiver and the received data.

The transmitter block is equipped with an 8 bit wide TX data

register. It is possible to write 8 bits into the register in burst

mode and the internal bit rate generator transmits the bits out

with the predefined rate.

It is also possible to store the received data bits into a FIFO

register and read them out in a buffered mode.

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