2.7 Fault (FLTb) Pin

FLTb is an open-drain type output. Once the UVLO condition is cleared on the driver side of the device, the FLTb pin is released. A

pull-up resistor takes the pin high. When the desaturation condition is detected, the Si828x indicates the fault by bringing the FLTb pin

low. FLTb stays low until the controller brings the RSTb pin low.

FLTb is also taken low if the UVLO condition is met during device operation. FLTb is released in that case as soon as the UVLO condi-

tion is cleared.

2.8 Reset (RSTb) Pin

The RSTb pin is used to clear the desaturation condition and bring the Si828x driver back to an operational state. Even though the input

may be toggling, the driver will not change state until the fault condition has been reset.

2.9 Undervoltage Lockout (UVLO)

The UVLO circuit unconditionally drives VL low when VDDB is below the lockout threshold. The Si828x is maintained in UVLO until

2.10 Ready (RDY) Pin (Si8285 Only)

The ready pin indicates to the controller that power is available on both sides of the isolation, i.e., at VDDA and VDDB. RDY goes high

when both the primary side and secondary side UVLO circuits are disengaged. If the UVLO conditions are met on either side of the

isolation barrier, the ready pin will return low. RDY is a push-pull output pin and can be floated if not used.

2.11 Miller Clamp

IGBT power circuits are commonly connected in a half bridge configuration with the collector of the bottom IGBT tied to the emitter of

the top IGBT.

When the upper IGBT turns on (while the bottom IGBT is in the off state), the voltage on the collector of the bottom IGBT flies up sever-

a positive gate voltage spike and can turn on the bottom IGBT. This behavior is called Miller parasitic turn on and can be destructive to

the switch since it causes shoot through current from the rail right across the two IGBTs to ground. The Si828x Miller clamp’s purpose

VL

VH

Driver Control

2.0 V

CLMP

Driver Control

Soft Shutdown

VSSB

VSSB

VSSB

VDDB

Figure 2.4. Miller Clamp Device

The Miller clamp device (Clamp) is engaged after the main driver had been on (VL) and pulled IGBT gate voltage close to VSSB, such

that one can consider the IGBT being already off. This timing prevents the Miller clamp from interfering with the driver’s operation. The

engaging of the Miller Clamp is done by comparing the IGBT gate voltage with a 2.0 V reference (relative to VSSB) before turning on

the Miller clamp NMOS.

Si8285/86 Data Sheet

System Overview

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