LOGIC DIAGRAM

VCC1 = PIN 1

VCC2 = PIN 16

VEE = PIN 8

Q0

Q1

Q2

Q3

3

D0

2Q0

5

G0

7

D1

4

CE

13

CC

12

CE

9

D2

14

D3

6Q1

11 Q2

15 Q3

10

G1

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

3–13

REV 6

9/96

Quad Latch

The MC10133 is a high speed, low power, quad latch consisting of four

bistable latch circuits with D type inputs and gated Q outputs, allowing direct

wiring to a bus. When the clock is high, outputs will follow D inputs. Information

is latched on the negative going transition of the clock.

The outputs are gated when the output enable (G) is low. All four latches may

be clocked at one time with the common clock (CC), or each half may be

clocked separately with its clock enable (CE).

PD = 310 mW typ/pkg (No Load)

tpd = 4.0 ns typ

tr, tf = 2.0 ns typ (20%–80%)

TRUTH TABLE

G

C

D

Qn+1

H

X

X

L

L

L

X

Qn

L

H

L

L

L

H

H

H

C = CC + CE

MC10133

DIP

PIN ASSIGNMENT

VCC1

Q0

D0

CE

G0

Q1

D1

VEE

VCC2

Q3

D3

CC

CE

Q2

G1

D2

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

L SUFFIX

CERAMIC PACKAGE

CASE 620–10

P SUFFIX

PLASTIC PACKAGE

CASE 648–08