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AD9163 Folha de dados(PDF) 1 Page - Analog Devices |
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AD9163 Folha de dados(HTML) 1 Page - Analog Devices |
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1 / 124 page  16-Bit, 12 GSPS, RF DAC and Digital Upconverter Data Sheet AD9163 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com FEATURES DAC update rate up to 12 GSPS (minimum) Direct RF synthesis at 6 GSPS (minimum) DC to 3 GHz in nonreturn-to-zero (NRZ)mode DC to 6 GHz in 2× NRZ mode 1.5 GHz to 7.5 GHz in Mix-Mode Selectable interpolation 6×, 8×, 12×, 16×, 24× Excellent dynamic performance APPLICATIONS Broadband communications systems DOCSIS 3.1 cable modem termination system (CMTS)/ video on demand (VOD)/edge quadrature amplitude modulation (EQAM) Wireless communications infrastructure MC-GSM, W-CDMA, LTE, LTE-A, point to point GENERAL DESCRIPTION The AD91631 is a high performance, 16-bit digital-to-analog converter (DAC) that supports data rates to 6 GSPS. The DAC core is based on a quad-switch architecture coupled with a 2× interpolator filter that enables an effective DAC update rate of up to 12 GSPS in some modes. The high dynamic range and bandwidth makes this DAC ideally suited for the most demanding high speed radio frequency (RF) DAC applications. Superior RF performance and deep interpolation rates enable use of the AD9163 in many wireless infrastructure applications, including MC-GSM, W-CDMA, LTE, and LTE-A. The wide bandwidth of up to 1 GHz and the complex NCO and digital upconverter enable dual band and triple band direct RF synthesis of wireless infrastructure signals, eliminating costly analog upconverters. Wide analog bandwidth capability combines with high dynamic range to support DOCSIS 3.1 cable infrastructure compliance from the minimum of one carrier up to 1 GHz of signal bandwidth, making it ideal for cable multiple dwelling unit (MDU) applications. A 2× interpolator filter (FIR85) enables the AD9163 to be config- ured for lower data rates and converter clocking to reduce the overall system power and ease the filtering requirements. In Mix-Mode™ operation, the AD9163 can reconstruct RF carriers in the second and third Nyquist zones up to 7.5 GHz while still maintaining exceptional dynamic range. The output current can be programmed from 8 mA to 38.76 mA. The AD9163 data interface consists of up to eight JESD204B serializer/deserializer (SERDES) lanes that are programmable in terms of lane speed and number of lanes to enable application flexibility. A serial peripheral interface (SPI) configures the AD9163 and monitors the status of all the registers. The AD9163 is offered in a 169-ball, 11 mm × 11 mm, 0.8 mm pitch CSP_BGA package. PRODUCT HIGHLIGHTS 1. High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 7.5 GHz. 2. Up to eight lanes JESD204B SERDES interface, flexible in terms of number of lanes and lane speed. 3. Bandwidth and dynamic range to meet multiband wireless communications standards with margin. FUNCTIONAL BLOCK DIAGRAM HB 2× HB 3× JESD HB 2×, 4×, 8× INV SINC SDO SDIO SCLK CS SPI DAC CORE SERDIN0± SERDIN7± SYSREF± SYNCOUT± CLOCK DISTRIBUTION CLK± AD9163 TO JESD TO DATAPATH TX_ENABLE OUTPUT± RESET IRQ VREF ISET VREF NCO HB 2× NRZ RZ MIX Figure 1. 1 Protected by U.S. Patents 6,842,132 and 7,796,971. |
Nº de peça semelhante - AD9163 |
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Descrição semelhante - AD9163 |
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