AM50DL128BG70I datasheet(4/64 Pages) AMD

Nome de Peças	AM50DL128BG70I

Descrição Electrónicos	Stacked Multi-Chip Package (MCP) Flash Memory and SRAM

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Fabricante Electrônico	AMD [Advanced Micro Devices]

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4 / 64 page

January 8, 2003

Am50DL128BG

3

PR E L I M I N A R Y

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5

MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5

Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7

Special Package Handling Instructions .................................... 7

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9

MCP Device Bus Operations . . . . . . . . . . . . . . . . 10

Table 1. Device Bus Operations—Flash Word Mode, CIOf = VIH .. 11

Table 2. Device Bus Operations—Flash Byte Mode, CIOf = V

IL ..... 12

Flash Device Bus Operations . . . . . . . . . . . . . . . 13

Word/Byte Configuration ........................................................ 13

Requirements for Reading Array Data ................................... 13

Writing Commands/Command Sequences ............................ 13

Accelerated Program Operation .......................................... 13

Autoselect Functions ........................................................... 13

Simultaneous Read/Write Operations with Zero Latency ....... 13

Standby Mode ........................................................................ 14

Automatic Sleep Mode ........................................................... 14

RESET#: Hardware Reset Pin ............................................... 14

Output Disable Mode .............................................................. 14

Table 3. Am29DL640G Sector Architecture ....................................15

Table 4. Bank Address ....................................................................18

Table 5. SecSi

 Sector Addresses ...............................................18

Sector/Sector Block Protection and Unprotection .................. 19

Table 6. Am29DL640G Boot Sector/Sector Block Addresses for Pro-

tection/Unprotection ........................................................................19

Write Protect (WP#) ................................................................ 19

Table 7. WP#/ACC Modes ..............................................................20

Temporary Sector Unprotect .................................................. 20

Figure 1. Temporary Sector Unprotect Operation........................... 20

Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 21

SecSi™ (Secured Silicon) Sector

Flash Memory Region ............................................................ 22

Figure 3. SecSi Sector Protect Verify.............................................. 23

Hardware Data Protection ...................................................... 23

Low V

CC Write Inhibit ........................................................... 23

Write Pulse “Glitch” Protection ............................................ 23

Logical Inhibit ...................................................................... 23

Power-Up Write Inhibit ......................................................... 23

Common Flash Memory Interface (CFI) . . . . . . . 23

Table 8. CFI Query Identification String .......................................... 24

System Interface String................................................................... 24

Table 10. Device Geometry Definition ............................................ 25

Table 11. Primary Vendor-Specific Extended Query ...................... 26

Flash Command Definitions . . . . . . . . . . . . . . . . 27

Reading Array Data ................................................................ 27

Reset Command ..................................................................... 27

Autoselect Command Sequence ............................................ 27

Enter SecSi™ Sector/Exit SecSi Sector

Command Sequence .............................................................. 27

Byte/Word Program Command Sequence ............................. 28

Unlock Bypass Command Sequence .................................. 28

Figure 4. Program Operation .......................................................... 29

Chip Erase Command Sequence ........................................... 29

Sector Erase Command Sequence ........................................ 29

Erase Suspend/Erase Resume Commands ........................... 30

Figure 5. Erase Operation.............................................................. 30

Table 12. Am29DL640G Command Definitions .............................. 31

Flash Write Operation Status . . . . . . . . . . . . . . . 32

DQ7: Data# Polling ................................................................. 32

Figure 6. Data# Polling Algorithm .................................................. 32

RY/BY#: Ready/Busy# ............................................................ 33

DQ6: Toggle Bit I .................................................................... 33

Figure 7. Toggle Bit Algorithm........................................................ 33

DQ2: Toggle Bit II ................................................................... 34

Reading Toggle Bits DQ6/DQ2 ............................................... 34

DQ5: Exceeded Timing Limits ................................................ 34

DQ3: Sector Erase Timer ....................................................... 34

Table 13. Write Operation Status ................................................... 35

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 36

Figure 8. Maximum Negative Overshoot Waveform ...................... 36

Figure 9. Maximum Positive Overshoot Waveform........................ 36

Flash DC Characteristics . . . . . . . . . . . . . . . . . . 37

CMOS Compatible .................................................................. 37

Figure 10. I

CC1 Current vs. Time (Showing Active and

Automatic Sleep Currents) ............................................................. 39

Figure 11. Typical I

CC1 vs. Frequency ............................................ 39

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 12. Test Setup.................................................................... 40

Figure 13. Input Waveforms and Measurement Levels ................. 40

pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 41

CE#s Timing ........................................................................... 41

Figure 14. Timing Diagram for Alternating

Between Pseudo SRAM to Flash................................................... 41

Read-Only Operations ........................................................... 42

Figure 15. Read Operation Timings ............................................... 42

Hardware Reset (RESET#) .................................................... 43

Figure 16. Reset Timings ............................................................... 43

Word/Byte Configuration (CIOf) .............................................. 44

Figure 17. CIOf Timings for Read Operations................................ 44

Figure 18. CIOf Timings for Write Operations................................ 44

Erase and Program Operations .............................................. 45

Figure 19. Program Operation Timings.......................................... 46

Figure 20. Accelerated Program Timing Diagram.......................... 46

Figure 21. Chip/Sector Erase Operation Timings .......................... 47

Figure 22. Back-to-back Read/Write Cycle Timings ...................... 48

Figure 23. Data# Polling Timings (During Embedded Algorithms). 48

Figure 24. Toggle Bit Timings (During Embedded Algorithms)...... 49

Figure 25. DQ2 vs. DQ6................................................................. 49

Temporary Sector Unprotect .................................................. 50

Figure 26. Temporary Sector Unprotect Timing Diagram .............. 50

Figure 27. Sector/Sector Block Protect and

Unprotect Timing Diagram ............................................................. 51

Alternate CE#f Controlled Erase and Program Operations .... 52

Figure 28. Flash Alternate CE#f Controlled Write (Erase/Program)

Operation Timings.......................................................................... 53

Read Cycle ............................................................................. 54

Figure 29. Psuedo SRAM Read Cycle........................................... 54

Figure 30. Page Read Timing ........................................................ 55

Write Cycle ............................................................................. 56

Figure 31. Pseudo SRAM Write Cycle—WE# Control ................... 56

Figure 32. Pseudo SRAM Write Cycle—CE1#s Control ................ 57

Figure 33. Pseudo SRAM Write Cycle—

UB#s and LB#s Control.................................................................. 58

Nº de peça semelhante - AM50DL128BG70I

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Advanced Micro Devices	AM50DL128BH	959Kb / 68P	Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
SPANSION	AM50DL128BH	1Mb / 70P	Two Am29DL640G 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories
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Advanced Micro Devices	AM50DL128BH56IS	959Kb / 68P	Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
SPANSION	AM50DL128BH56IS	1Mb / 70P	Two Am29DL640G 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories

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