CDCEL937PWR datasheet(7/39 Pages) TI1

Nome de Peças	CDCEL937PWR

Descrição Electrónicos	Flexible Low Power LVCMOS Clock Generator With SSC Support For EMI Reduction

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Fabricante Electrônico	TI1 [Texas Instruments]

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CDCE937, CDCEL937

www.ti.com

SLAS564G – AUGUST 2007 – REVISED OCTOBER 2016

Product Folder Links: CDCE937 CDCEL937

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Electrical Characteristics (continued)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP(1)

MAX

UNIT

(2)

10000 cycles.

(3)

Jitter depends on configuration. Data is taken under the following conditions: 1-PLL is fIN = 27 MHz and Y2/3 = 27 MHz (measured at

Y2); 3-PLL is fIN = 27 MHz, Y2/3 = 27 MHz (measured at Y2), Y4/5 = 16.384 MHz, and Y6/7 = 74.25 MHz.

(4)

The tsk(o) specification is only valid for equal loading of each bank of outputs, and outputs are generated from the same divider; data

taking on rising edge (tr).

(5)

odc depends on output rise and fall time (tr/tf).

(6)

SDA and SCL pins are 3.3-V tolerant.

tjit(cc)

Cycle-to-cycle jitter(2)(3)

1 PLL switching, Y2-to-Y3

60

90

ps

3 PLL switching, Y2-to-Y7

100

150

tjit(per)

Peak-to-peak period jitter(3)

1 PLL switching, Y2-to-Y3

70

100

ps

3 PLL switching, Y2-to-Y7

120

180

tsk(o)

Output skew(4) (see Table 2)

fOUT = 50 MHz, Y1-to-Y3

60

ps

fOUT = 50 MHz, Y2-to-Y5

160

odc

Output duty cycle(5)

fVCO = 100 MHz, Pdiv = 1

45%

55%

CDCE937 – LVCMOS FOR Vddout = 2.5 V

VOH

LVCMOS high-level output voltage

Vddout = 2.3 V, IOH = –0.1 mA

2.2

V

Vddout = 2.3 V, IOH = –6 mA

1.7

Vddout = 2.3 V, IOH = –10 mA

1.6

VOL

LVCMOS low-level output voltage

Vddout = 2.3 V, IOL = 0.1 mA

0.1

V

Vddout = 2.3 V, IOL = 6 mA

0.5

Vddout = 2.3 V, IOL = 10 mA

0.7

tPLH, tPHL

Propagation delay

All PLL bypass

3.4

ns

tr/tf

Rise and fall time

Vddout = 2.5 V (20%–80%)

0.8

ns

tjit(cc)

Cycle-to-cycle jitter(2)(3)

1 PLL switching, Y2-to-Y3

60

90

ps

3 PLL switching, Y2-to-Y7

100

150

tjit(per)

Peak-to-peak period jitter(4)

1 PLL switching, Y2-to-Y3

70

100

ps

3 PLL switching, Y2-to-Y7

120

180

tsk(o)

Output skew(4)

(see Table 2)

fOUT = 50 MHz, Y1-to-Y3

60

ps

fOUT = 50 MHz, Y2-to-Y5

160

odc

Output duty cycle(5)

f(VCO) = 100 MHz, Pdiv = 1

45%

55%

CDCEL937 – LVCMOS FOR Vddout = 1.8 V

VOH

LVCMOS high-level output voltage

Vddout = 1.7 V, IOH = –0.1 mA

1.6

V

Vddout = 1.7 V, IOH = –4 mA

1.4

Vddout = 1.7 V, IOH = –8 mA

1.1

VOL

LVCMOS low-level output voltage

Vddout = 1.7 V, IOL = 0.1 mA

0.1

V

Vddout = 1.7 V, IOL = 4 mA

0.3

Vddout = 1.7 V, IOL = 8 mA

0.6

tPLH, tPHL

Propagation delay

All PLL bypass

2.6

ns

tr/tf

Rise and fall time

Vddout= 1.8 V (20%–80%)

0.7

ns

tjit(cc)

Cycle-to-cycle jitter(2)(3)

1 PLL switching, Y2-to-Y3

70

120

ps

3 PLL switching, Y2-to-Y7

100

150

tjit(per)

Peak-to-peak period jitter(3)

1 PLL switching, Y2-to-Y3

90

140

ps

3 PLL switching, Y2-to-Y7

120

190

tsk(o)

Output skew(4)

(see Table 2)

fOUT = 50 MHz, Y1-to-Y3

60

ps

fOUT = 50 MHz, Y2-to-Y5

160

odc

Output duty cycle(5)

f(VCO) = 100 MHz, Pdiv = 1

45%

55%

SDA AND SCL

VIK

SCL and SDA input clamp voltage

VDD = 1.7 V; II = –18 mA

–1.2

V

IIH

SCL and SDA input current

VI = VDD; VDD = 1.9 V

±10

µA

VIH

SDA/SCL input high voltage(6)

0.7 × VDD

V

VIL

SDA/SCL input low voltage(6)

0.3 × VDD

V

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