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SL2610LH2N Folha de dados(PDF) 6 Page - Zarlink Semiconductor Inc |
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SL2610LH2N Folha de dados(HTML) 6 Page - Zarlink Semiconductor Inc |
6 / 27 page SL2610 Data Sheet 6 Zarlink Semiconductor Inc. 2.0 Programming The SL2610 is controlled by an I2C data bus and is compatible with both standard and fast mode formats. Data and Clock are fed in on the SDA and SCL lines respectively as defined by I2C bus format. The synthesizer can either accept data (write mode) or send data (read mode). The LSB of the address byte (R/W) sets the device into write mode if it is low and read mode if it is high. Tables 2 and 3 illustrate the format of the data. The device can be programmed to respond to several addresses, which enables the use of more than one synthesizer in an I2C bus system (Tables 2 and 3). Table 4 shows how the address is selected by applying a voltage to the ‘ADD’ input. When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period and during following acknowledge periods after further data bytes are received. When the device is programmed into read mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line low during this period the device generates an internal STOP condition which inhibits further reading. 2.1 Write mode With reference to Table 2, bytes 2 and 3 contain frequency information bits 214-20 inclusive. Byte 4 controls the reference divider ratio bits R4-R0 (Table 1) and the charge pump setting bits C1-C0 (Table 6). Byte 5 controls the IF select (Table 8), the band select function bits BS1-BS0 (Table 7), the switching ports P3-P0 and the test modes (Table 5). After reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines whether the byte is interpreted as a byte 2 or 4, a logic '0' indicating byte 2 and a logic '1' indicating byte 4. Having interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively. Having received two complete data bytes, additional data bytes can be entered, where byte interpretation follows the same procedure, without re-addressing the device. This procedure continues until a STOP condition is received. The STOP condition can be generated after any data byte, if however it occurs during a byte transmission, the previous byte data is retained. To facilitate smooth fine tuning, the frequency data bytes are only accepted by the device after all 15 bits of frequency data have been received, or after the generation of a STOP condition. 2.2 Read mode When the device is in read mode, the status byte read from the device takes the form shown Table 3. Bit 1 (POR) is the power-on reset indicator, and this is set to a logic '1' if the Vcc supply to the device has dropped below 3V (at 25oC), e.g., when the device is initially turned ON. The POR is reset to '0' when the read sequence is terminated by a STOP command. When POR is set high this indicates that the programmed information may have been corrupted and the device reset to power up condition. Bit 2 (FL) indicates whether the device is phase locked, a logic '1' is present if the device is locked and a logic '0' if the device is unlocked. |
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