ST10F273Z4Q3 datasheet(9/188 Pages) STMICROELECTRONICS

Nome de Peças	ST10F273Z4Q3

Descrição Electrónicos	16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAM

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Fabricante Electrônico	STMICROELECTRONICS [STMicroelectronics]

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9 / 188 page

ST10F273Z4

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9/188

List of figures

Figure 1.

ST10F273 Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 2.

Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 3.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 4.

Flash structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 5.

CPU block diagram (MAC unit not included) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 6.

MAC unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 7.

X-Interrupt basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 8.

Block diagram of GPT1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 9.

Block diagram of GPT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 10.

Block diagram of PWM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 11.

Connection to single CAN bus via separate CAN transceivers . . . . . . . . . . . . . . . . . . . . . 75

Figure 12.

Connection to single CAN bus via common CAN transceivers. . . . . . . . . . . . . . . . . . . . . . 75

Figure 13.

Connection to two different CAN buses (e.g. for gateway application). . . . . . . . . . . . . . . . 76

Figure 14.

Connection to one CAN bus with internal Parallel mode enabled . . . . . . . . . . . . . . . . . . . 76

Figure 15.

Asynchronous power-on RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 16.

Asynchronous power-on RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 17.

Asynchronous hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Figure 18.

Asynchronous hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Figure 19.

Synchronous short / long hardware RESET (EA = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 20.

Synchronous short / long hardware RESET (EA = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 21.

Synchronous long hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 22.

Synchronous long hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Figure 23.

SW / WDT unidirectional RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Figure 24.

SW / WDT unidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 25.

SW / WDT bidirectional RESET (EA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 26.

SW / WDT bidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 27.

SW / WDT bidirectional RESET (EA=0) followed by a HW RESET . . . . . . . . . . . . . . . . . . 97

Figure 28.

Minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 29.

System reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 30.

Internal (simplified) reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figure 31.

Example of software or watchdog bidirectional reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . 100

Figure 32.

Example of software or watchdog bidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . 101

Figure 33.

PORT0 bits latched into the different registers after reset . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 34.

External RC circuitry on RPD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 35.

Port2 test mode structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Figure 36.

Supply current versus the operating frequency (RUN and IDLE modes) . . . . . . . . . . . . . 132

Figure 37.

A/D conversion characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Figure 38.

A/D converter input pins scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 39.

Charge sharing timing diagram during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Figure 40.

Anti-aliasing filter and conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Figure 41.

Input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Figure 42.

Float waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Figure 43.

Generation mechanisms for the CPU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Figure 44.

ST10F273 PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Figure 45.

Crystal oscillator and resonator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 46.

32 kHz crystal oscillator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

Figure 47.

External clock drive XTAL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

Figure 48.

External memory cycle: Multiplexed bus, with/without read/write delay, normal ALE. . . . 158

Nº de peça semelhante - ST10F273Z4Q3

Fabricante Electrônico	Nome de Peças	Folha de dados	Descrição Electrónicos
STMicroelectronics	ST10F273Z4Q3	2Mb / 179P	16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAM

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Descrição semelhante - ST10F273Z4Q3

Fabricante Electrônico	Nome de Peças	Folha de dados	Descrição Electrónicos
STMicroelectronics	ST10F273E	1Mb / 179P	16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAM
	ST10F273	2Mb / 179P	16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAM
	ST10F280	2Mb / 239P	16-bit MCU with MAC unit, 512 Kbyte Flash memory and 18 Kbyte RAM
	ST10F271Z1	3Mb / 185P	16-bit MCU with 128 Kbyte Flash memory and 12 Kbyte RAM
	ST10F272Z2	2Mb / 189P	16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
	ST10F271	2Mb / 173P	16-bit MCU with 128 Kbyte Flash memory and 12 Kbyte RAM
	ST10F272	3Mb / 179P	16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
	ST10F272M	3Mb / 175P	16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
	ST10F272M	1Mb / 176P	16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
	ST10F271B	1Mb / 180P	16-bit MCU with 128 Kbyte Flash memory and 8/12 Kbyte RAM

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