TP11368N datasheet(4/18 Pages) NSC

Nome de Peças	TP11368N

Descrição Electrónicos	Octal Adaptive Differential PCM Processor

Download	18 Pages

Scroll/Zoom	100%

Fabricante Electrônico	NSC [National Semiconductor (TI)]

Página de início	http://www.national.com

Logo

4 / 18 page

Functional Description (Continued)

The TP11368 is capable of processing 16 independent chan-

nels (half duplex) or 8 full-duplex PCM channels within 125

µs (8 kHz).

The logic state of TRB at the falling edge of CE determines

which input register is active during that CE period and which

output register will be active in the following third CE period.

The input data is processed (PCM data encoded or ADPCM

data decoded) during the second cycle and shifted out in the

third cycle of CE while CE is high.

SERIAL I/O

Input data is transferred into the TP11368 on the falling edge

of the clock signal, while output data is transmitted on the ris-

ing edge of the clock signal. PCM data is transferred syn-

chronously using PSCK, while ADPCM data is transferred

synchronously using ASCK. The clock signals ASCK and

PSCK should be high while CE changes. All serial data is

transferred with MSB first.

Figure 2 and Figure 3 show the

serial input and output structures, respectively.

PCM Serial Input Register

The serial PCM data to be encoded is shifted into the 8-bit

PCM input register with the falling edges of PSCK while CE

and TRB are high. The falling edge of CE latches the state of

the input register and transfers the last 8 bits data prior to the

CE transition to the core for processing. The 8-bit PCM input

register is cleared asynchronously with RSTB going low.

ADPCM Serial Input Register

The ADPCM serial input register is a 5-bit shift register to

store the 5-bit data in the 40 kbps ADPCM mode. Serial input

data is latched in with the falling edges of ASCK while CE is

high and TRB is low. A minimum number of five low going

ASCK pulses must be available within the CE pulse when

operating in the 40 kbps mode. For the 32, 24 and 16 kbps

modes, a minimum of four low going ASCK pulses must be

available while CE is high. The falling edge of CE latches the

last 5 bits data in the 40 kbps mode or the last 4 bits data in

the 32, 24, and 16 kbps modes prior to the CE transistion.

See

Table 3 for the position of the ADPCM data in the 5-bit

input register when 5 ASCK low going pulses occur while CE

is high and TRB is low. Note that bit 1 in

Table 3 is the LSB.

ADPCM Output Register

The internal encoded parallel ADPCM data is loaded into the

5-bit ADPCM output register with the falling edge of CE sig-

nal. The first MSB data is shifted out after the rising edge of

CE, subsequent ADPCM serial data is shifted out with the

rising edge of ASCK.

Table 4 shows the transfer order of the

ADPCM output data. If more than 4 ASCK clocks are avail-

able while CE is high in the 32, 24, and 16 kbps modes, the

ADPCM output data will recirculate starting with the MSB. In

the case of the 40 kbps mode, the ADPCM output pattern will

recirculate, starting with the MSB, with the fifth rising edge of

ASCK while CE is high.

PCM Output Register

The decoded 8-bit parallel PCM data is loaded into an 8-bit

parallel-to-serial output shift register with the falling edge of

CE. The MSB data is shifted out with the leading edge of CE,

and subsequent data are shifted out with the rising edges of

PSCK while CE is high. The 8-bit PCM data at the RSO out-

put will recirculate with the MSB first after the seventh rising

edge of PSCK while CE is high.

Figure 4 shows the full duplex timing diagram for the 40 kbps

mode. For the 32, 24 and 16 kbps modes only four ASCK low

pulses are needed while CE is high (see

Figure 5).

TRB is alternate high and low in the full duplex mode at each

falling edge of CE for a transmit (encoder) operation followed

DS012902-4

FIGURE 2. Serial Input Structure

www.national.com

4

Nº de peça semelhante - TP11368N

Fabricante Electrônico	Nome de Peças	Folha de dados	Descrição Electrónicos
Texas Instruments	TP11368	634Kb / 20P	[Old version datasheet] Octal Adaptive Differential PCM Processor
	TP11368V/NOPB	634Kb / 20P	[Old version datasheet] Octal Adaptive Differential PCM Processor
	TP11368	634Kb / 20P	[Old version datasheet] Octal Adaptive Differential PCM Processor

More results

Descrição semelhante - TP11368N

Fabricante Electrônico	Nome de Peças	Folha de dados	Descrição Electrónicos
Texas Instruments	TP11368	634Kb / 20P	[Old version datasheet] Octal Adaptive Differential PCM Processor
National Semiconductor ...	TP11362A	442Kb / 16P	Quad Adaptive Differential PCM Processor
Integrated Device Techn...	IDT821068	589Kb / 45P	OCTAL PROGRAMMABLE PCM CODEC
Integrated Device Techn...	IDT82V1068	539Kb / 56P	OCTAL PROGRAMMABLE PCM CODEC
OKI electronic componet...	MSM7731-01	247Kb / 43P	Multifunction PCM CODEC (Voice Signal Processor)
Texas Instruments	LM339X2	84Kb / 4P	[Old version datasheet] OCTAL DIFFERENTIAL COMPARATOR
Ultralife Corporation.	UBP103450	466Kb / 2P	PCM Rev: L
Sanyo Semicon Device	LA7451M	190Kb / 11P	Two-Channel, Noise Reduction Processor for 8-mm VCR PCM
Integrated Circuit Syst...	ICS94241	141Kb / 16P	Programmable TCH??for Differential PIII??Processor
Maxim Integrated Produc...	MAX9924	527Kb / 23P	Variable Reluctance Sensor Interfaces with Differential Input and Adaptive Peak Threshold Rev 2; 3/09

More results

TP11368N Folha de dados(PDF) 4 Page - National Semiconductor (TI)

TP11368N Folha de dados(HTML) 4 Page - National Semiconductor (TI)

Nº de peça semelhante - TP11368N

Descrição semelhante - TP11368N

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Folha de dados Download

Ligação URL