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AD9886KS-140 Folha de dados(PDF) 10 Page - Analog Devices

Nome de Peças AD9886KS-140
Descrição Electrónicos  Analog Interface for Flat Panel Displays
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Página de início  http://www.analog.com
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AD9886
–10–
DESIGN GUIDE
General Description
The AD9886 is a fully integrated solution for capturing analog
RGB signals and digitizing them for display on flat panel monitors
or projectors. The circuit is ideal for providing a computer
interface for HDTV monitors or as the front end to high-
performance video scan converters.
Implemented in a high-performance CMOS process, the inter-
face can capture signals with pixel rates of up to 140 MHz and
with an Alternate Pixel Sampling mode, up to 280 MHz.
The AD9886 includes all necessary input buffering, signal dc
restoration (clamping), offset and gain (brightness and contrast)
adjustment, pixel clock generation, sampling phase control,
and output data formatting. All controls are programmable via
a 2-wire serial interface. Full integration of these sensitive analog
functions makes system design straightforward and less sensi-
tive to the physical and electrical environment.
With a typical power dissipation of less than 750 mW and an
operating temperature range of 0
°C to 70°C, the device requires
no special environmental considerations.
Input Signal Handling
The AD9886 has three high-impedance analog input pins for
the Red, Green, and Blue channels. They will accommodate
signals ranging from 0.5 V to 1.0 V p-p.
Signals are typically brought onto the interface board via a
DVI-I connector, a 15-pin D connector, or via BNC connectors.
The AD9886 should be located as close as practical to the
input connector. Signals should be routed via matched-imped-
ance traces (normally 75
Ω) to the IC input pins.
At that point the signal should be resistively terminated (75
to the signal ground return) and capacitively coupled to the
AD9886 inputs through 47 nF capacitors. These capacitors
form part of the dc restoration circuit.
In an ideal world of perfectly matched impedances, the best
performance can be obtained with the widest possible signal
bandwidth. The ultrawide bandwidth inputs of the AD9886
(330 MHz) can track the input signal continuously as it moves
from one pixel level to the next, and digitize the pixel during a
long, flat pixel time. In many systems, however, there are mis-
matches, reflections, and noise, which can result in excessive
ringing and distortion of the input waveform. This makes it
more difficult to establish a sampling phase that provides good
image quality. It has been shown that a small inductor in series
with the input is effective in rolling off the input bandwidth
slightly, and providing a high quality signal over a wider range
of conditions. Using a Fair-Rite #2508051217Z0 High-Speed
Signal Chip Bead inductor in the circuit of Figure 1 gives good
results in most applications.
RGB
INPUT
RAIN
GAIN
BAIN
47nF
75
Figure 1. Analog Input Interface Circuit
HSYNC, VSYNC Inputs
The AD9886 takes a horizontal sync signal, which is used to
generate the pixel clock and clamp timing. It is possible to oper-
ate the AD9886 without applying HSYNC (using an external
clock, external clamp, and single port output mode) but a number
of features of the chip will be unavailable, so it is recommended
that HSYNC be provided. This can be either a sync signal
directly from the graphics source, or a preprocessed TTL or
CMOS level signal.
The HSYNC input includes a Schmitt trigger buffer for immunity
to noise and signals with long rise times. In typical PC-based
graphic systems, the sync signals are simply TTL-level drivers
feeding unshielded wires in the monitor cable. As such, no ter-
mination is required or desired.
Serial Control Port
The serial control port is designed for 3.3 V logic. If there are
5 V drivers on the bus, these pins should be protected with
150
Ω series resistors placed between the pull-up resistors and
the input pins.
Output Signal Handling
The digital outputs are designed and specified to operate from a
3.3 V power supply (VDD). They can also work with a VDD as
low as 2.5 V for compatibility with other 2.5 V logic.
Clamping
RGB Clamping
To properly digitize the incoming signal, the dc offset of the
input must be adjusted to fit the range of the on-board A/D
converters.
Most graphics systems produce RGB signals with black at
ground and white at approximately 0.75 V. However, if sync
signals are embedded in the graphics, the sync tip is often at
ground and black is at 300 mV. Then white is at approximately
1.0 V. Some common RGB line amplifier boxes use emitter-
follower buffers to split signals and increase drive capability.
This introduces a 700 mV dc offset to the signal, which must be
removed for proper capture by the AD9886.
The key to clamping is to identify a portion (time) of the signal
when the graphic system is known to be producing black. An
offset is then introduced which results in the A/D converters
producing a black output (code 00h) when the known black
input is present. The offset then remains in place when other
signal levels are processed, and the entire signal is shifted to
eliminate offset errors.
In most graphics systems, black is transmitted between active
video lines. Going back to CRT displays, when the electron
beam has completed writing a horizontal line on the screen (at
the right side), the beam is quickly deflected to the left side of
the screen (called horizontal retrace) and a black signal is pro-
vided to prevent the beam from disturbing the image.
In systems with embedded sync, a blacker-than-black signal
(HSYNC) is produced briefly to signal the CRT that it is time
to begin a retrace. For obvious reasons, it is important to avoid
clamping on the tip of HSYNC. Fortunately, there is virtually
always a period following HSYNC called the back porch where
a good black reference is provided. This is the time when clamp-
ing should be done.


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