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TP3076 Folha de dados(PDF) 4 Page - National Semiconductor (TI) |
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TP3076 Folha de dados(HTML) 4 Page - National Semiconductor (TI) |
4 / 18 page Functional Description (Continued) vices (COMBO); time-slots begin nominally coincident with the rising edge of the appropriate FS input. The alternative is to use Delayed Data mode, which is similar to shortframe sync timing on COMBO, in which each FS input must be high at least a half-cycle of BCLK earlier than the timeslot. The Time-Slot Assignment circuit on the device can only be used with Delayed Data timing. When using Time-Slot Assignment, the beginning of the first time-slot in a frame is identified by the appropriate FS input. The actual transmit and receive time-slots are then deter- mined by the internal Time-Slot Assignment counters. Transmit and Receive frames and time-slots may be skewed from each other by any number of BCLK cycles. During each assigned Transmit time-slot, the D X1 output shifts data out from the PCM register on the rising edges of BCLK. TS X1 also pulls low for the first 71⁄2 bit times of the time-slot to con- trol the TRI-STATE Enable of a backplane line-driver. Serial PCM data is shifted into the D R1 input during each assigned Receive time-slot on the falling edges of BCLK. SERIAL CONTROL PORT Control information and data are written into or read-back from COMBO II via the serial control port consisting of the control clock CCLK, the serial data input, CI, and output, CO, and the Chip Select input, CS. All control instructions require 2 bytes, as listed Table 1, with the exception of a single byte power-up/down command. The Byte 1 bits are used as fol- lows: bit 7 specifies power up or power down; bits 6, 5, 4 and 3 specify the register address, bit 2 specifies whether the in- struction is read or write; bit 1 specifies a one or two byte in- struction; and bit 0 is not used. To shift control data into COMBO II, CCLK must be pulsed high 8 times while CS is low. Data on the CI input is shifted into the serial input register on the falling edge of each CCLK pulse. After all data is shifted in, the contents of the input shift register are decoded, and may indicate that a 2nd byte of control data will follow. This second byte may either be de- fined by a second byte-wide CS pulse or may follow the first contiguously, i.e, it is not mandatory for CS to return high be- tween the first and second control bytes. At the end of CCLK8 in the 2nd control byte the data is loaded into the ap- propriate programmable register. CS may remain low con- tinuously when programming successive registers, if de- sired. However, CS must be set high when no data transfers are in progress. To readback Interface Latch data or status information from COMBO II, the first byte of the appropriate instruction is strobed while CS is low, as defined in Table 1. CS must be kept low, or be taken low again for a further 8 CCLK cycles, during which the data is shifted onto the CO pin on the rising edges of CCLK. When CS is high the CO pin is in the high-impedance TRI-STATE, enabling the CI and CO pins of many devices to be multiplexed together. If CS returns high during either byte 1 or byte 2 before all eight CCLK pulses of that byte occur, both the bit count and byte count are reset and register contents are not affected. This prevents loss of synchronization in the control interface as well as corruption of register data due to processor inter- rupt or other problem. When CS returns low again, the de- vice will be ready to accept bit 1 of byte 1 of a new instruc- tion. Programmable Functions POWER-UP/DOWN CONTROL Following power-on initialization, power-up and power-down control may be accomplished by writing any of the control in- structions listed in Table 1 into COMBO II with the “P” bit set to “0” for power-up or “1” for power-down. Normally it is rec- ommended that all programmable functions be initially pro- grammed while the device is powered down. Power state control can then be included with the last programming in- struction or the separate single-byte instruction. Any of the programmable registers may also be modified while the de- vice is powered-up or down by setting the “P” bit as indi- cated. When the power-up or down control is entered as a single byte instruction, bit one (1) must be reset to a 0. When a power-up command is given, all de-activated circuits are activated, but the TRI-STATE PCM output(s), D X1 will re- main in the high impedance state until the second FS X pulse after power-up. CONTROL REGISTER INSTRUCTION The first byte of a READ or WRITE instruction to the Control Register is as shown in Table 1. The second byte has the fol- lowing bit functions: TABLE 2. Control Register Byte 2 Functions Bit Number and Name 76543210 Function F1 F0 MA IA DN DL AL PP 0 0 MCLK = 512 kHz 0 1 MCLK = 1.536 MHz or 1.544 MHz 1 0 MCLK = 2.048 MHz (Note 4) 1 1 MCLK = 4.096 MHz 0 X Select µ255 Law (Note 4) 1 0 A-Law, Including Even Bit Inversion 1 1 A-Law, No Even Bit Inversion 0 Delay Data Timing 1 Non-Delayed Data Timing (Note 4) 0 0 Normal Operation (Note 4) 1 X Digital Loopback 0 1 Analog Loopback 0 Power Amp Enabled in PDN 1 Power Amp Disabled in PDN (Note 4) Note 4: state at power-on initialization. Master Clock Frequency Selection A Master clock must be provided to COMBO II for operation of the filter and coding/decoding functions. The MCLK fre- quency must be either 512 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, or 4.096 MHz and must be synchronous with BCLK. Bits F 1 and F0 (see Table 2) must be set during initial- ization to select the correct internal divider. www.national.com 4 |
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