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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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TSC2007I Folha de dados(PDF) 8 Page - Texas Instruments |
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TSC2007I Folha de dados(HTML) 8 Page - Texas Instruments |
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8 / 41 page  TSC2007 SBAS405A – MARCH 2007 – REVISED MARCH 2009...................................................................................................................................................... www.ti.com TIMING REQUIREMENTS: I 2C High-Speed Mode (SCL = 3.4MHz) All specifications typical at –40°C to +85°C, VDD = 1.6V, unless otherwise noted. 2-WIRE HIGH-SPEED MODE PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT SCL clock frequency fSCL 0 3.4 MHz Hold time (repeated) START condition tHD, STA 160 ns Low period of SCL clock tLOW 160 ns High period of the SCL clock tHIGH 60 ns Setup time for a repeated START condition tSU, STA 160 ns Data hold time tHD, DAT 0 70 ns Data setup time tSU, DAT 10 ns Rise time for SCL signal (receiving) tR Cb = total bus capacitance 10 40 ns Rise time for SDA signal (receiving) tR Cb = total bus capacitance 10 80 ns Fall time for SCL signal (receiving) tF Cb = total bus capacitance 10 40 ns Fall time for SDA signal (receiving) tF Cb = total bus capacitance 10 80 ns Fall time for both SDA and SCL signals (transmitting) tF Cb = total bus capacitance 10 80 ns Setup time for STOP condition tSU, STO 160 ns Capacitive load for each bus line Cb Cb = total capacitance of one bus line in pF 100 pF 8 bits 40 SCL + 127 CCLK, VDD = 1.8V 46.5 µs Cycle time 12 bits 49 SCL + 148 CCLK, VDD = 1.8V 95.3 µs 8 bits VDD = 1.8V 21.52 kSPS Effective throughput 12 bits VDD = 1.8V 10.49 kSPS 8 bits VDD = 1.8V 150.65 kHz Equivalent rate = effective throughput × 7 12 bits VDD = 1.8V 73.46 kHz 8 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): TSC2007 |
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