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5V41236PGGI Folha de dados(PDF) 5 Page - Integrated Device Technology

Nome de Peças 5V41236PGGI
Descrição Electrónicos  4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER
Download  18 Pages
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Fabricante Electrônico  IDT [Integrated Device Technology]
Página de início  http://www.idt.com
Logo IDT - Integrated Device Technology

5V41236PGGI Folha de dados(HTML) 5 Page - Integrated Device Technology

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IDT5V41236
4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER
IDT® 4 OUTPUT PCIE GEN1/2/3 SYNTHESIZER
5
IDT5V41236
APRIL 4, 2017
Output Structures
General PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed.
1. Each 0.01µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible.
2. No vias should be used between decoupling capacitor
and VDD pin.
3. The PCB trace to VDD pin should be kept as short as
possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from the
device is less critical.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (any ferrite beads and bulk decoupling capacitors can
be mounted on the back). Other signal traces should be
routed away from the IDT5V41236.This includes signal
traces just underneath the device, or on layers adjacent to
the ground plane layer used by the device.
R
R
475
6*IREF
=2.3 mA
IREF
See Output Termination
Sections - Pages 3 ~ 5


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