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AD9261 Folha de dados(PDF) 9 Page - Analog Devices |
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AD9261 Folha de dados(HTML) 9 Page - Analog Devices |
9 / 29 page AD9261 Rev. 0 | Page 8 of 28 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 CLK– CVDD PDWN DVDD DGND DRVDD PLL_LOCKED DCO D0 D1 D2 D3 NOTES 1. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE FOR THE LFCSP PACKAGE. SOLDERING THE EXPOSED PADDLE TO THE PCB INCREASES THE RELIABILITY OF THE SOLDER JOINTS, MAXIMIZING THE THERMAL CAPACITY OF THE PACKAGE. PLLMULT1/SDIO PLLMULT2 PLLMULT3 PLLMULT4 DVDD DGND DRVDD OR D15 D14 D13 35 PLLMULT0/SCLK 36 34 33 32 31 30 29 28 27 26 25 AD9261 TOP VIEW (Not to Scale) PIN 1 INDICATOR Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. Mnemonic Description 1 CLK− Clock Input (−). 2 CVDD Clock Supply (1.8 V). 3 PDWN External Power-Down Pin. 4, 19, 31 DVDD Digital Supply (1.8 V). 5, 18, 30 DGND Digital Ground. 6, 17, 29 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V). 7 PLL_LOCKED PLL Lock Indicator. 8 DCO Data Clock Output. 9 to 16, 20 to 27 D0 to D15 Data Output Bits. D0 is the LSB and D15 is the MSB. 28 OR Overrange Indicator. 32, 33, 34 PLLMULT4, PLLMULT3, PLLMULT2 PLL Mode Selection Pins. 35 PLLMULT1/SDIO PLL Mode Selection Pin/Serial Port Interface Data Input/Output. 36 PLLMULT0/SCLK PLL Mode Selection Pin/Serial Port Interface Clock. 37 CSB Serial Port Interface Chip Select. Active low. 38, 46 AGND Analog Ground. 39, 42, 45 AVDD Analog Supply (1.8 V). 40 VREF Voltage Reference Input/Output. 41 CFILT Noise Limiting Filter Capacitor. 43 VIN+ Analog Input (+). 44 VIN– Analog Input (−). 47 CGND Clock Ground. 48 CLK+ Clock Input (+). 49 EPAD Analog Ground. Pin 49 is the exposed thermal pad on the bottom of the package. |
Nº de peça semelhante - AD9261 |
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Descrição semelhante - AD9261 |
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