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UPD48288118AF1 Folha de dados(PDF) 4 Page - Renesas Technology Corp

Nome de Peças UPD48288118AF1
Descrição Electrónicos  288M-BIT Low Latency DRAM
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Fabricante Electrônico  RENESAS [Renesas Technology Corp]
Página de início  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD48288118AF1 Folha de dados(HTML) 4 Page - Renesas Technology Corp

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µµµµPD48288118AF1
R10DS0255EJ0101 Rev. 1.01
Page 4 of 51
Jan. 15, 2016
Pin Description
(1/2)
Symbol
Type
Description
CK, CK#
Input
Clock inputs:
CK and CK# are differential clock inputs. This input clock pair registers address and control inputs
on the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.
CS#
Input
Chip select
CS# enables the commands when CS# is LOW and disables them when CS# is HIGH. When the
command is disabled, new commands are ignored, but internal operations continue.
WE#, REF#
Input
WRITE command pin, Refresh command pin:
WE#, REF# are sampled at the positive edge of CK, WE#, and REF# define (together with CS#) the
command to be executed.
A0–A20
Input
Address inputs:
A0–A20 define the row and column addresses for READ and WRITE operations. During a MODE
REGISTER SET, the address inputs define the register settings. They are sampled at the rising
edge of CK.
A20 is reserved for address expansion. This expansion address can be treated as address input, but
it does not affect the operation of the device.
A21–A22
Input
Reserved for future use:
These signals should be tied to VSS or leave open.
BA0–BA2
Input
Bank address inputs;
Select to which internal bank a command is being applied.
D0–D17
Input
Data input:
The D signals form the 18-bit input data bus. During WRITE commands, the data is referenced to
both edges of DK.
.
.
Q0–Q17
Output
Data output:
The Q signals form the 18-bit output data bus. During READ commands, the data is referenced to
both edges of QK.
.
.
QKx, QKx#
Output
Output data clocks:
QKx and QKx# are opposite polarity, output data clocks. They are always free running and edge-
aligned with data output from the
µPD48288118AF1. QKx# is ideally 180 degrees out of phase with
QKx.
QK0 and QK0# are aligned with Q0–Q8. QK1 and QK1# are aligned with Q9–Q17.
DK, DK#
Input
Input data clock;
DK and DK# are the differential input data clocks. All input data is referenced to both edges of DK.
DK# is ideally 180 degrees out of phase with DK.
All Ds are referenced to DK and DK#.
DM
Input
Input data mask;
The DM signal is the input mask signal for WRITE data. Input data is masked when DM is sampled
HIGH along with the WRITE input data. DM is sampled on both edges of DK. The signal should be
VSS if not used.
QVLD
Output
Data valid;
The QVLD indicates valid output data. QVLD is edge-aligned with QKx and QKx#.


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