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CS35L32 Folha de dados(PDF) 11 Page - Cirrus Logic |
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CS35L32 Folha de dados(HTML) 11 Page - Cirrus Logic |
11 / 51 page DS963F5 11 CS35L32 3 Characteristics and Specifications Table 3-7. Signal Monitoring Characteristics Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, amp gain = 12 dB, 0.1- sense resistor, GNDA = GNDP = 0 V, TA = +25°C. Measurement bandwidth is 20 Hz to 20 kHz, Fs = 48 kHz, Input Signal = 1 kHz, MCLKINT = 6 MHz, MCLKINT is explained in Section 4.13.1 and Section 7.7. Parameters Min Typical Max Units General ADC characteristics Power-up time: tPUP(ADC) —8.5 [1] 1.Typical value is specified with PDN_AMP and PDN_xMON bits initially set. Maximum power-up time is affected by the actual MCLKINT frequency. ms VSENSE± monitoring characteristics (VMON) Data width — 16 — Bits Dynamic range (unweighted), VSENSE± = ±5.0 V (10 VPP)— 60 — dB 2 2.Parameters given in dB are referred to the applicable typical full-scale voltages. Applies to all THD+N and resolution values in the table Total harmonic distortion + noise, –3.8 dBFS 3 3.VSENSE± THD is measured with the Class D amplifier as the audio source connected to an 8- + 33H speaker load, supplied by a 6.3-VPP, 1-kHz sine wave, operating under the typical performance test conditions to produce a large, unclipped audio signal. This setup produces a –3.8-dBFS VMON output. Larger Class D amplifier amplitudes begin to exhibit clipping behavior, increasing distortion of the signal supplied to VSENSE± — –60 — dB 2 Full-scale signal input voltage 6.59•VA 6.94•VA 7.29•VA VPP Common-mode rejection ratio (217 Hz @ 500 mVPP) 4 4.CMRR test setup for VSENSE±: —60— dB 2 Group delay 5 5.VMON group delay is measured from the time a signal is presented on the VSENSE± and pins until the MSB of the digitized signal exits the serial port. Fs is the LRCK rate. —7.6/Fs— s ISENSE± monitoring characteristics (IMON) Data width — 16 — Bits Dynamic range (unweighted), ISENSE± = ±0.625 A (1.25 APP)— 56 — dB 2 Total harmonic distortion, –29.5 dBFS 6 6.For reference, injecting a 125-mVpp fully differential sine wave into the ISENSE± pins (equivalent to a ±0.625 A current with a 0.1- ISENSE resistor) produces an IMON output of –29.5 dBFS (since typical full-scale is 1.64*VA, in VPP). ISENSE± monitoring THD is measured using the Class D amplifier as the audio source, which is connected to an 8- + 33-H speaker load, supplied by a 7.0-VPP, 1-kHz sine wave, operating under the typical performance test conditions to produce a large, unclipped audio signal. This setup produces a –29.5-dBFS amplitude IMON output. Larger Class D amplifier amplitudes begin to exhibit clipping behavior, increasing the distortion of the signal supplied to ISENSE±. — –45 — dB 2 Full-scale signal input voltage 1.56•VA 1.64•VA 1.72•VA VPP VMON-to-IMON isolation 7 7. VMON-to-IMON isolation is the error in the current sense due to VMON, expressed relative to full-scale sense current in decibels. —56— dB 2 Group delay 8 8.IMON group delay is measured from when a signal is presented on the ISENSE± pins until the MSB of the digitized signal exits the serial port. Fs is the LRCK rate. —7.6/Fs— s VP monitoring characteristics Data width — 8 — Bits Voltage resolution (See the equation in Section 4.8.4.) — 35.3 — mV (FF code) signal input voltage (VP) 2.89•VA 3.05•VA 3.20•VA V VPMON = 1011 0011 VPMON = 1011 0100 … VPMON = 1111 1111 VPMON = 0000 0000 — — … — — 2.8 2.835 … 5.482 5.518 — — … — — V V … V V Table 3-8. Digital Interface Specifications and Characteristics Test conditions, except where noted otherwise: VA = 1.8 V, VP = 3.6 V, VBST = 5.0 V, GNDA = GNDP = 0 V, TA = +25°C. Parameters Symbol Test Conditions Min Max Units Input leakage current (per pin) 1,2 1.Specification includes current through internal pull up/down resistors, where applicable (as defined in Section 1). 2.Leakage current is measured with VA = 1.80 V, VP = 3.60 V, VBST = 3.60 V, and RESET asserted. Each pin is tested while driven high and low. FLOUT2/AD0 FLEN, FLINH, LRCK MCLK, SCLK, SDOUT SCL, SDA, INT, RESET IIN — — — — — — — — ±7.5 ±4.5 ±4.5 ±0.1 A A A A Input capacitance IIN — — 10 pF VA logic I/Os High-level output voltage VOH IOH = –67/–100 A 3 3.For the ADSP output SDOUT and potential outputs SCLK and LRCK (if M/S = 1), if ADSP_DRIVE = 0 see Section 7.13, IOH and IOL are –100 and +100 A. If ADSP_DRIVE = 1, IOH and IOL are –67 and +67 A. For other, non-ADSP_DRIVE-affected outputs, IOH and IOLare –100 and +100 A. VA–0.2 — V Low-level output voltage VOL All outputs, IOL = 67/100 A 3 INT, SDA, IOL = 3 mA — — 0.20 0.4 V V High-level input voltage VIH —0.70•VA — V Low-level input voltage VIL — — 0.30•VA V VSENSE+ 217 Hz 500 mVPP DC Offset = 0 VSENSE– |
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