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FIN1217MTD Folha de dados(PDF) 10 Page - Fairchild Semiconductor |
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FIN1217MTD Folha de dados(HTML) 10 Page - Fairchild Semiconductor |
10 / 17 page www.fairchildsemi.com 10 FIGURE 1. Differential LVDS Output DC Test Circuit Note A: For all input pulses, tR or tF < = 1 ns. Note B: CL includes all probe and jig capacitance. FIGURE 2. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit TABLE 2. Receiver Minimum and Maximum Input Threshold Test Voltages Applied Voltages Resulting Differential Input Voltage Resulting Common Mode Input Voltage (V) (mV) (V) VIA VIB VID VIC 1.25 1.15 100 1.2 1.15 1.25 −100 1.2 2.4 2.3 100 2.35 2.3 2.4 −100 2.35 0.1 0 100 0.05 00.1 −100 0.05 1.5 0.9 600 1.2 0.9 1.5 −600 1.2 2.4 1.8 600 2.1 1.8 2.4 −600 2.1 0.6 0 600 0.3 00.6 −600 0.3 |
Nº de peça semelhante - FIN1217MTD |
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Descrição semelhante - FIN1217MTD |
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