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DM505MRABF Folha de dados(PDF) 4 Page - Texas Instruments

Nome de Peças DM505MRABF
Descrição Electrónicos  SoC for Vision Analytics 15mm Package (ABF) Silicon Revision 2.0
Download  290 Pages
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Fabricante Electrônico  TI1 [Texas Instruments]
Página de início  http://www.ti.com
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DM505MRABF Folha de dados(HTML) 4 Page - Texas Instruments

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DM505
SPRS976D – NOVEMBER 2016 – REVISED JULY 2017
www.ti.com
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Table of Contents
Copyright © 2016–2017, Texas Instruments Incorporated
Table of Contents
1
Device Overview
......................................... 1
1.1
Features
............................................. 1
1.2
Applications
........................................... 2
1.3
Description
............................................ 2
1.4
Functional Block Diagram
........................... 3
2
Revision History
......................................... 5
3
Device Comparison
..................................... 6
3.1
Device Comparison Table
............................ 6
4
Terminal Configuration and Functions
.............. 8
4.1
Pin Diagram
.......................................... 8
4.2
Pin Attributes
......................................... 8
4.3
Signal Descriptions
.................................. 39
4.4
Pin Multiplexing
..................................... 65
4.5
Connections for Unused Pins
....................... 76
5
Specifications
........................................... 77
5.1
Absolute Maximum Ratings
......................... 77
5.2
ESD Ratings
........................................ 78
5.3
Power on Hour (POH) Limits
........................ 78
5.4
Recommended Operating Conditions
............... 79
5.5
Operating Performance Points
...................... 81
5.6
Power Consumption Summary
...................... 90
5.7
Electrical Characteristics
............................ 90
5.8
Thermal Characteristics
............................. 96
5.9
Timing Requirements and Switching
Characteristics
....................................... 98
6
Detailed Description
.................................. 175
6.1
Description
......................................... 175
6.2
Functional Block Diagram
......................... 175
6.3
DSP Subsystem
................................... 176
6.4
IPU
................................................. 181
6.5
EVE
................................................ 182
6.6
Memory Subsystem
................................ 184
6.7
Interprocessor Communication
.................... 187
6.8
Interrupt Controller
................................. 188
6.9
EDMA
.............................................. 188
6.10
Peripherals
......................................... 190
6.11
On-Chip Debug
.................................... 202
7
Applications, Implementation, and Layout
...... 206
7.1
Introduction
........................................ 206
7.2
Power Optimizations
............................... 207
7.3
Core Power Domains
.............................. 218
7.4
Single-Ended Interfaces
........................... 227
7.5
Differential Interfaces
.............................. 230
7.6
Clock Routing Guidelines
.......................... 232
7.7
LPDDR2 Board Design and Layout Guidelines
.... 233
7.8
DDR2 Board Design and Layout Guidelines
....... 242
7.9
DDR3 Board Design and Layout Guidelines
....... 254
7.10
CVIDEO/SD-DAC Guidelines and Electrical
Data/Timing
........................................ 277
8
Device and Documentation Support
.............. 279
8.1
Device Nomenclature
.............................. 279
8.2
Tools and Software
................................ 281
8.3
Documentation Support
............................ 281
8.4
Receiving Notification of Documentation Updates
. 282
8.5
Community Resources
............................. 282
8.6
Trademarks
........................................ 282
8.7
Electrostatic Discharge Caution
................... 283
8.8
Export Control Notice
.............................. 283
8.9
Glossary
............................................ 283
9
Mechanical Packaging Information
............... 284
9.1
Mechanical Data
................................... 284


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