TQFP Pin Description

Symbol

Type

Description

I

Address field LSBs and Address Counter preset Inputs

A

I

Address Inputs

I/O

Data Input and Output pins

NC

No Connect

BW

I

Byte Write—Writes all enabled bytes; active low

I

I

CK

I

Clock Input Signal; active high

GW

I

Global Write Enable—Writes all bytes; active low

I

Chip Enable; active low

G

I

Output Enable; active low

ADV

I

Burst address counter advance enable; active low

ADSP, ADSC

I

Address Strobe (Processor, Cache Controller); active low

ZZ

I

Sleep Mode control; active high

FT

I

Flow Through or Pipeline mode; active low

LBO

I

Linear Burst Order mode; active low

I

Core power supply

I

I/O and Core Ground

I

Output driver power supply

NC

—

No Connect

NU

—

Not Used—There is an internal chip connection to these pins, but they are unused by the device. They may be

GS8128018/32/36GT-400/333/250/200

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.01 5/2017

5/23

© 2015, GSI Technology