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DAC38RF83 Folha de dados(PDF) 11 Page - Texas Instruments |
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DAC38RF83 Folha de dados(HTML) 11 Page - Texas Instruments |
11 / 155 page 11 DAC38RF80, DAC38RF83, DAC38RF84 DAC38RF85, DAC38RF90, DAC38RF93 www.ti.com SLASEA3C – DECEMBER 2016 – REVISED JULY 2017 DAC38RF83 DAC38RF93 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Pin Functions - DAC38RF80, DAC38RF90, DAC38RF84 PIN I/O DESCRIPTION NAME NO. AGND C11, C12, D11, E11, F12, J12, K11, L11, M11, M12, D12, L12 - Analog ground. ALARM K8 O CMOS output for ALARM condition. Default polarity is active low, but can be changed to active high via RESET_CONFIG alm_out_pol control bit. AMUX0 G3 O Analog test pin for SerDes, Lane 0 to Lane 3. Can be left floating. AMUX1 F3 O Analog test pin for SerDes, Lane 4 to Lane 7. Can be left floating. ATEST C8 O Analog test pin for DAC, references and PLL. Can be left floating. CLKTX+ A7 O Divided output clock, internal 100 Ω differential termination, self-biased, positive terminal. CLKTX- A6 O Divided output clock, internal 100 Ω differential termination, self-biased, negative terminal. DACCLK+ A10 I Device clock, internal 100 Ω differential termination, self-biased, positive terminal. DACCLK- A9 I Device clock, internal 100 Ω differential termination, self-biased, negative terminal. DACCLKSE A12 I Single ended device clock optional input. Can be left floating if not used. internal 50 Ω termination DGND A2, B2, C2, D2, D6, E2, E7, F2, F6, G2, G7, H6, J7, K2, L2, L3, L4, L5, M6 - Digital ground. EXTIO C10 Requires a 0.1 μF decoupling capacitor to AGND. GPI0 L6 Factory use only. User should GND. GPI1 M7 Factory use only. User should GND. GPO0 L7 Used for CMOS SYNC0\ signal. GPIO1 K7 Used for CMOS SYNC1\ signal. IFORCE D3 Test pin for on chip parametrics. Can be left floating. RBIAS C9 I/O Full-scale output current bias. Change the full-scale output current through DACFS in register DACFS (8.5.72). Expected to be 3.6 kΩ to GND for 40 mA full scale output. RESET K9 I Active low input for chip RESET, which resets all the programming registers to their default state. Internal pull-up. RX0+ J1 I CML SerDes interface lane 0 input, positive RX0- K1 I CML SerDes interface lane 0 input, negative RX1+ M1 I CML SerDes interface lane 1 input, positive RX1- L1 I CML SerDes interface lane 1 input, negative RX2+ M2 I CML SerDes interface lane 2 input, positive RX2- M3 I CML SerDes interface lane 2 input, negative RX3+ M5 I CML SerDes interface lane 3 input, positive RX3- M4 I CML SerDes interface lane 3 input, negative RX4+ H1 I CML SerDes interface lane 4 input, positive RX4- G1 I CML SerDes interface lane 4 input, negative RX5+ E1 I CML SerDes interface lane 5 input, positive RX5- F1 I CML SerDes interface lane 5 input, negative RX6+ D1 I CML SerDes interface lane 6 input, positive RX6- C1 I CML SerDes interface lane 6 input, negative RX7+ A1 I CML SerDes interface lane 7 input, positive RX7- B1 I CML SerDes interface lane 7 input, negative SCLK L9 I Serial interface clock. Internal pull-down. SDEN M8 I Active low serial data enable, always an input to the DAC38RFxx. Internal pull-up. SDIO M10 I/O Serial interface data. Bi-directional in 3-pin mode (default) and uni-directional input 4-pin mode. Internal pull-down. SDO M9 O Uni-directional serial interface data output in 4-pin mode. The SDO pin is tri-stated in 3-pin interface mode (default). SLEEP L8 I Active high asynchronous hardware power-down input. Internal pull-down. SYNC0+ C4 O Synchronization request to transmitter for JESD204B link 0, LVDS positive output. SYNC0- C3 O Synchronization request to transmitter for JESD204B link 0, LVDS negative output. SYNC1+ C7 O Synchronization request to transmitter for JESD204B link 1, LVDS positive output. SYNC1- C6 O Synchronization request to transmitter for JESD204B link 1, LVDS negative output. |
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