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SM65MLVD203D Folha de dados(PDF) 5 Page - Texas Instruments |
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SM65MLVD203D Folha de dados(HTML) 5 Page - Texas Instruments |
5 / 10 page SN65MLVD201, SN65MLVD203 SN65MLVD206, SN65MLVD207 SLLS558A – DECEMBER 2002 – JUNE 2003 www.ti.com 5 BUS INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS (continued) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT CAB Transceiver with driver disabled differential input capacitance VAB = 0.4 sin (30E6πt)V (2) 3 pF CA/B Transceiver with driver disabled input capacitance balance, (CA/CB) 0.99 1.01 (1) All typical values are at 25 °C and with a 3.3-V supply voltage. (2) HP4194A impedance analyzer (or equivalent) DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT tpLH Propagation delay time, low-to-high-level output 1 1.5 2.4 ns tpHL Propagation delay time, high-to-low-level output 1 1.5 2.4 ns tr Differential output signal rise time See Figure 5 1 1.6 ns tf Differential output signal fall time See Figure 5 1 1.6 ns tsk(p) Pulse skew (|tpHL – tpLH|) 0 100 ps tsk(pp) Part-to-part skew 1 ns tjit(per) Period jitter, rms (1 standard deviation) (2) 100 MHz clock input(3) 2 3 ps tjit(pp) Peak-to-peak jitter(2)(5) 200 Mbps 215–1 PRBS input(4) 30 130 ps tpHZ Disable time, high-level-to-high-impedance output 7 ns tpLZ Disable time, low-level-to-high–impedance output See Figure 6 7 ns tpZH Enable time, high-impedance-to-high-level output See Figure 6 7 ns tpZL Enable time, high-impedance-to-low-level output 7 ns (1) All typical values are at 25 °C and with a 3.3-V supply voltage. (2) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers. (3) tr = tf = 0.5 ns (10% to 90%), measured over 30 k samples. (4) tr = tf = 0.5 ns (10% to 90%), measured over 100 k samples. (5) Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)). RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT tpLH Propagation delay time, low-to-high-level output 2 4 6 ns tpHL Propagation delay time, high-to-low-level output 2 4 6 ns tr Output signal rise time 1 2.3 ns tf Output signal fall time CL = 15 pF, See Figure 10 1 2.3 ns t Pulse skew (|t t|) Type 1 L ,g 100 300 ps tsk(p) Pulse skew (|tpHL – tpLH|) Type 2 300 500 ps tsk(pp) Part-to-part skew(2) 1 ns tjit(per) Period jitter, rms (1 standard deviation) (3) 100 MHz clock input(4) 4 7 ps t Peak to peak jitter(3)(6) Type 1 200 Mbps 215 1 PRBS input(5) 300 700 ps tjit(pp) Peak-to-peak jitter(3)(6) Type 2 200 Mbps 215–1 PRBS input(5) 450 800 ps tpHZ Disable time, high-level-to-high-impedance output 10 ns tpLZ Disable time, low-level-to-high-impedance output See Figure 11 10 ns tpZH Enable time, high-impedance-to-high-level output See Figure 11 15 ns tpZL Enable time, high-impedance-to-low-level output 15 ns (1) All typical values are at 25 °C and with a 3.3-V supply voltage. (2) HP4194A impedance analyzer (or equivalent) (3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers. (4) VID = 200 mVpp (LVD201, 203), VID = 400 mVpp (LVD206, 207), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 30 k samples. (5) VID = 200 mVpp (LVD201, 203), VID = 400 mVpp (LVD206, 207), Vcm = 1 V, tr = tf = 0.5 ns (10% to 90%), measured over 100 k samples. (6) Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)). |
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