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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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RT5509 Folha de dados(PDF) 48 Page - Richtek Technology Corporation |
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RT5509 Folha de dados(HTML) 48 Page - Richtek Technology Corporation |
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48 / 58 page  RT5509 Copyright © 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation www.richtek.com DS5509-00 August 2017 48 ADDR Byte Bits R/W Name Description Default 0xA3 3 23:0 R spk_rpt[23:0] Format : Q0.23, please refer to spk_rpt_sel 0xA4 3 23:0 R/W nDelay[23:0] The delay added to the output voltage of SPKFB for synchronization. nDelay = reg[0xa4] / 2^21 The range is [ 2, 3) with 21 fractional bits. 0 0xA5 3 23:0 R/W res[23:0] The initial value of the parameter which is propositional to the resistance. Resistance = reg[0xa5] / 2^23 The range is [0, 2) with 23 fractional bits. 24'h800000 0xA6 3 23:0 R/W phi1[23:0] The initial value of the radians for the adaptive filter. The radians π/2 is normalized to 1/2, and the range is [ 0.5, 0.5] with 23 fractional bits. Phi1 c = reg[a6] / 2^23 * pi 24'hC4266F 0xA7 3 23:0 R/W phi2[23:0] 24'h345F58 0xA8 3 23:0 R/W phi3[23:0] 24'hFE21CB 0xA9 3 23:0 R/W phi4[23:0] 24'h000000 0xAA 3 23:0 R/W phi5[23:0] 24'h000000 0xAB 3 23:0 R/W Adptive_b0[23:0] The initial value of the expansion coefficient for the adaptive filter. The range is [ 2, 2) with 22 fractional bits. B0 = reg[ab] / 2^22 24'h10221 0xAC 3 23:0 R/W Adptive_b1[23:0] 24'hF1EBC8 0xAD 3 23:0 R/W Adptive_b2[23:0] 24'h33BD58 0xAE 3 23:0 R/W Adptive_b3[23:0] 24'h309E9 0xAF 3 23:0 R/W Adptive_b4[23:0] 24'h000000 0xB0 3 23:0 R/W Adptive_b5[23:0] 24'h000000 0xB4 1 7 R/W OTP_PLL_LOCK_IGNOR E Access MTP memory without PLL lock 0 5:4 R/W D_IB_IDAC2 Boost block Bias current option 00 = 1.25 01 = 2.5 10 = 3.75 11 = 5 2'b01 3 R/W TDM_EN I2S TDM enable bit 0 2 R/W TDM_ADC_SEL I2S ADC TDM slot selection 0 1 R/W TDM_DAC_SEL I2S DAC TDM slot selection 0 0 R/W dcrEstInSilMod Do DCR estimation when act signal is not logic 0 0 0xCF 1 7:0 R/W DRC_MIN_GAIN 8'hFF 0xD0 1 7:4 R/W Reserved 2'b00 3:0 R/W DRC_SET_SEL[3:0] 0000 : DRC1 0001 : DRC2 0010 : DRC3 0011 : DRC4 0100 : DRC5 other : no define 4'h0 |
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Descrição semelhante - RT5509 |
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