Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.02c 8/2017

8/33

© 2011, GSI Technology

GS8662D20/38BD-550/500/450/400/350

GS8662D06/11BD-500/450/400/350

FLXDrive-II Output Driver Impedance Control

HSTL I/O SigmaQuad-II+ SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to

5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is

between 175

 and 350. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts

in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and

temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance

evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is

implemented with discrete binary weighted impedance steps.

Input Termination Impedance Control

These SigmaQuad-II+ SRAMs are supplied with programmable input termination on Data (D), Byte Write (BW), and Clock (K/K)

input receivers. Input termination can be enabled or disabled via the ODT pin (6R). When the ODT pin is tied Low (or left

floating —the pin has a small pull-down resistor), input termination is disabled. When the ODT pin is tied High, input termination

program output driver impedance, and is nominally RQ*0.6 Thevenin-equivalent when RQ is between 175

 and 250. Periodic

readjustment of the termination impedance occurs to compensate for drifts in supply voltage and temperature, in the same manner

as for driver impedance (see above).

Note:

When ODT = 1, Data (D), Byte Write (BW), and Clock (K, K) input termination is always enabled. Consequently, D, BW, K, K

inputs should always be driven High or Low; they should never be tri-stated (i.e., in a High-Z state). If the inputs are tri-stated, the

to enter a meta-stable state and prevent the SRAM from operating within specification.