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ADV7179KCP Folha de dados(PDF) 7 Page - Analog Devices

Nome de Peças ADV7179KCP
Descrição Electrónicos  Chip Scale PAL/NTSC Video Encoder with Advanced Power Management
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ADV7174/ADV7179
Rev. A | Page 7 of 52
3.3 V TIMING SPECIFICATIONS
VAA = 3.0 V–3.6 V1, VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX2, unless otherwise noted.
Table 4.
Parameter
Conditions1
Min
Typ
Max
Unit
MPU PORT3, 4
SCLOCK Frequency
0
400
kHz
SCLOCK High Pulse Width, t1
0.6
µs
SCLOCK Low Pulse Width, t2
1.3
µs
Hold Time (Start Condition), t3
After this period, the first clock is generated
0.6
µs
Setup Time (Start Condition), t4
Relevant for repeated start condition
0.6
µs
Data Setup Time, t5
100
ns
SDATA, SCLOCK Rise Time, t6
300
ns
SDATA, SCLOCK Fall Time, t7
300
ns
Setup Time (Stop Condition), t8
0.6
µs
ANALOG OUTPUTS3, 5
Analog Output Delay
7
ns
DAC Analog Output Skew
0
ns
CLOCK CONTROL AND PIXEL PORT4, 5
fCLOCK
27
MHz
Clock High Time, t9
8
ns
Clock Low Time, t10
8
ns
Data Setup Time, t11
3.5
ns
Data Hold Time, t12
4
ns
Control Setup Time, t11
4
ns
Control Hold Time, t12
3
ns
Digital Output Access Time, t13
12
ns
Digital Output Hold Time, t14
8
ns
Pipeline Delay, tPD6
48
Clock Cycles
TELETEXT3, 4
Digital Output Access Time, t16
23
ns
Data Setup Time, t17
2
ns
Data Hold Time, t18
6
ns
RESET CONTROL3, 4
RESET Low Time
6
ns
1 The maximum/minimum specifications are guaranteed over this range. The maximum/minimum values are typical over 3.0 V to 3.6 V range.
2 Temperature range TMIN to TMAX: –40°C to +85°C.
3 TTL input values are 0 V to 3 V, with input rise/fall times −3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Analog output load –10 pF.
4 Guaranteed by characterization.
5 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6 See Figure 60.


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