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AD4020 Folha de dados(PDF) 1 Page - Analog Devices

Nome de Peças AD4020
Descrição Electrónicos  Precision SAR, Differential ADC
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
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AD4020 Folha de dados(HTML) 1 Page - Analog Devices

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20-Bit, 1.8 MSPS,
Precision SAR, Differential ADC
Data Sheet
AD4020
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
FEATURES
Throughput: 1.8 MSPS maximum
INL: ±3.1 ppm maximum
Guaranteed 20-bit no missing codes
Low power
9.0 mW at 1.8 MSPS (VDD only)
83 µW at 10 kSPS, 15 mW at 1.8 MSPS (total)
SNR: 100.5 dB typical at 1 kHz, 99 dB typical at 100 kHz
THD: −123 dB typical at 1 kHz, −100 dB typical at 100 kHz
Ease of use features reduce system power and complexity
Input overvoltage clamp circuit
Reduced nonlinear input charge kickback
High-Z mode
Long acquisition phase
Input span compression
Fast conversion time allows low SPI clock rates
SPI-programmable modes, read/write capability, status word
Differential analog input range: ±VREF
0 V to VREF with VREF from 2.4 V to 5.1 V
Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface
SAR architecture: no latency/pipeline delay
Valid first accurate conversion
Guaranteed operation: −40°C to +125°C
Serial interface: SPI/QSPI/MICROWIRE/DSP compatible
Ability to daisy-chain multiple ADCs and busy indicator
10-lead packages: 3 mm × 3 mm LFCSP, 3 mm × 4.90 mm MSOP
APPLICATIONS
Automatic test equipment
Machine automation
Medical equipment
Battery-powered equipment
Precision data acquisition systems
GENERAL DESCRIPTION
The AD4020 is a low noise, low power, high speed, 20-bit,
1.8 MSPS precision successive approximation register (SAR)
analog-to-digital converter (ADC). It incorporates ease of use
features that lower the signal chain power, reduce signal chain
complexity, and enable higher channel density. The high-Z mode,
coupled with a long acquisition phase, eliminates the need for a
dedicated high power, high speed ADC driver, thus broadening the
range of low power precision amplifiers that can drive this ADC
directly, while still achieving optimum performance. The input
span compression feature enables the ADC driver amplifier and the
ADC to operate off common supply rails without the need for a
negative supply while preserving the full ADC code range. The
low serial peripheral interface (SPI) clock rate requirement
reduces the digital input/output power consumption, broadens
processor options, and simplifies the task of sending data across
digital isolation.
Operating from a 1.8 V supply, the AD4020 has a ±VREF fully
differential input range with VREF ranging from 2.4 V to 5.1 V.
The AD4020 consumes only 15 mW at 1.8 MSPS with a minimum
SCK rate of 71 MHz in turbo mode and achieves ±3.1 ppm integral
nonlinearity (INL), guaranteed no missing codes at 20 bits with
100.5 dB typical signal-to-noise ratio (SNR). The reference voltage
is applied externally and can be set independently of the supply
voltage.
The SPI-compatible versatile serial interface features seven different
modes including the ability, using the SDI input, to daisy-chain
several ADCs on a single 3-wire bus, and provides an optional busy
indicator. The AD4020 is compatible with 1.8 V, 2.5 V, 3 V, and 5 V
logic, using the separate VIO supply.
The AD4020 is available in a 10-lead MSOP or a 10-lead LFCSP
with operation specified from −40°C to +125°C. The device is
pin compatible with the 18-bit, 2 MSPS AD4003.
FUNCTIONAL BLOCK DIAGRAM
GND
IN+
IN–
SDI
SCK
SDO
CNV
AD4020
20-BIT
SAR ADC
SERIAL
INTERFACE
VIO
REF
VDD
VREF
0
VREF
0
VREF/2
VREF/2
HIGH-Z
MODE
CLAMP
SPAN
COMPRESSION
TURBO
MODE
STATUS
BITS
2.5V TO 5V
1.8V
10µF
1.8V TO 5V
3-WIRE OR 4-WIRE
SPI INTERFACE
(DAISY CHAIN, CS)
Figure 1.


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