AD9246_17 datasheet(8/45 Pages) AD

Nome de Peças	AD9246

Descrição Electrónicos	1.8 V Analog-to-Digital Converter

Download	45 Pages

Scroll/Zoom	100%

Fabricante Electrônico	AD [Analog Devices]

Página de início	http://www.analog.com

Logo

8 / 45 page

AD9246

Rev. A | Page 7 of 44

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 2.5 V, unless otherwise noted.

Table 4.

AD9246BCPZ-80

AD9246BCPZ-105

AD9246BCPZ-125

Parameter1

Temp

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

CLOCK INPUT PARAMETERS

Conversion Rate, DCS Enabled

Full

20

80

20

105

20

125

MSPS

Conversion Rate, DCS Disabled

Full

10

80

10

105

10

125

MSPS

CLK Period

Full

12.5

9.5

8

ns

CLK Pulse Width High, DCS Enabled

Full

3.75

6.25

8.75

2.85

4.75

6.65

2.4

4

5.6

ns

CLK Pulse Width High, DCS Disabled

Full

5.63

6.25

6.88

4.28

4.75

5.23

3.6

4

4.4

ns

DATA OUTPUT PARAMETERS

Data Propagation Delay (tPD)2

Full

3.1

3.9

4.8

3.1

3.9

4.8

3.1

3.9

4.8

ns

DCO Propagation Delay (tDCO)

Full

4.4

ns

Setup Time (tS)

Full

4.9

5.7

3.4

4.3

2.6

3.5

ns

Hold Time (tH)

Full

5.9

6.8

4.4

5.3

3.7

4.5

ns

Pipeline Delay (Latency)

Full

12

cycles

Aperture Delay (tA)

Full

0.8

ns

Aperture Uncertainty (Jitter, tJ)

Full

0.1

ps rms

Wake-Up Time3

Full

350

μs

OUT-OF-RANGE RECOVERY TIME

Full

2

3

Cycles

SERIAL PORT INTERFACE4

SCLK Period (tCLK)

Full

40

ns

SCLK Pulse Width High Time (tHI)

Full

16

ns

SCLK Pulse Width Low Time (tLO)

Full

16

ns

SDIO to SCLK Setup Time (tDS)

Full

5

ns

SDIO to SCLK Hold Time (tDH)

Full

2

ns

CSB to SCLK Setup Time (tS)

Full

5

ns

CSB to SCLK Hold Time (tH)

Full

2

ns

1 See AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.

2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.

3 Wake-up time is dependent on the value of the decoupling capacitors, values shown with 0.1 μF capacitor across REFT and REFB.

4 See Figure 57 and the Serial Port Interface (SPI) section.

TIMING DIAGRAM

CLK+

DCO

DATA

N

N+ 1

N+ 2

N+ 3

N+ 4

N+ 5

N+ 6

N+ 7

N+ 8

N – 12

N – 11

N – 10

N – 9

N – 8

N – 7

N – 6

N – 5

N – 4

N – 13

CLK–

tCLK

tPD

tS

tH

tDCO

tCLK

tA

Figure 2. Timing Diagram

Nº de peça semelhante - AD9246_17

Fabricante Electrônico	Nome de Peças	Folha de dados	Descrição Electrónicos
Analog Devices	AD9246-105EB	1Mb / 44P	14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter REV. A
	AD9246-105EB	902Kb / 28P	High Speed ADC USB FIFO Evaluation Kit REV. 0
	AD9246-125EB	1Mb / 44P	14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter REV. A
	AD9246-125EB	902Kb / 28P	High Speed ADC USB FIFO Evaluation Kit REV. 0
	AD9246	1Mb / 44P	14-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter REV. A

More results

Descrição semelhante - AD9246_17

Fabricante Electrônico	Nome de Peças	Folha de dados	Descrição Electrónicos
Analog Devices	AD9266	1Mb / 33P	1.8 V Analog-to-Digital Converter
	AD9634	1Mb / 31P	1.8 V Analog-to-Digital Converter
	AD9601	972Kb / 33P	1.8 V Analog-to-Digital Converter
	AD9211	1Mb / 29P	1.8 V Analog-to-Digital Converter
	AD9626	1Mb / 37P	1.8 V Analog-to-Digital Converter
	AD9635	995Kb / 37P	1.8 V Analog-to-Digital Converter
	AD9637	1,012Kb / 41P	1.8 V Analog-to-Digital Converter
	AD9230	1Mb / 33P	1.8 V Analog-to-Digital Converter
	AD9257	1Mb / 41P	1.8 V Analog-to-Digital Converter
	AD9434	921Kb / 29P	1.8 V Analog-to-Digital Converter

More results

AD9246 Folha de dados(PDF) 8 Page - Analog Devices

AD9246 Folha de dados(HTML) 8 Page - Analog Devices

Nº de peça semelhante - AD9246_17

Descrição semelhante - AD9246_17

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Folha de dados Download

Ligação URL