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AD9259ABCPZRL7-50 Folha de dados(PDF) 8 Page - Analog Devices

Nome de Peças AD9259ABCPZRL7-50
Descrição Electrónicos  Serial LVDS 1.8 V ADC
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

AD9259ABCPZRL7-50 Folha de dados(HTML) 8 Page - Analog Devices

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Data Sheet
AD9259
Rev. E | Page 7 of 52
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4.
Parameter1, 2
Temp
Min
Typ
Max
Unit
CLOCK3
Maximum Clock Rate
Full
50
MSPS
Minimum Clock Rate
Full
10
MSPS
Clock Pulse Width High (tEH)
Full
10
ns
Clock Pulse Width Low (tEL)
Full
10
ns
OUTPUT PARAMETERS3
Propagation Delay (tPD)
Full
2.0
2.7
3.5
ns
Rise Time (tR) (20% to 80%)
Full
300
ps
Fall Time (tF) (20% to 80%)
Full
300
ps
FCO Propagation Delay (tFCO)
Full
2.0
2.7
3.5
ns
DCO Propagation Delay (tCPD)4
Full
tFCO +
(tSAMPLE/28)
ns
DCO to Data Delay (tDATA)4
Full
(tSAMPLE/28) − 300
(tSAMPLE/28)
(tSAMPLE/28) + 300
ps
DCO to FCO Delay (tFRAME)4
Full
(tSAMPLE/28) − 300
(tSAMPLE/28)
(tSAMPLE/28) + 300
ps
Data to Data Skew
(tDATA-MAX − tDATA-MIN)
Full
±50
±150
ps
Wake-Up Time (Standby)
25°C
600
ns
Wake-Up Time (Power-Down)
25°C
375
μs
Pipeline Latency
Full
8
CLK
cycles
APERTURE
Aperture Delay (tA)
25°C
500
ps
Aperture Uncertainty (Jitter)
25°C
<1
ps rms
Out-of-Range Recovery Time
25°C
2
CLK
cycles
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were
completed.
2
Measured on standard FR-4 material.
3
Can be adjusted via the SPI.
4
tSAMPLE/28 is based on the number of bits multiplied by 2; delays are based on half duty cycles.


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