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TS18 Folha de dados(PDF) 10 Page - Suntan Capacitors |
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TS18 Folha de dados(HTML) 10 Page - Suntan Capacitors |
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10 / 17 page  MULTILAYER CERAMIC CHIP CAPACITOR - SMD Suntan® TS18 5. Insulation Resistance Dielectrics Specification Testing Condition NPO/X7R/ X5R/Y5V More than 10 GΩ or 500Ω·F, whichever is smaller. Rated voltage for 60±5sec, at 25℃ 6. Dielectric Strength Dielectrics Specification Testing Condition NPO /X7R/X5R/Y5V No defects or abnormalities. No failure shall be observed when 300% (NPO);250%(X7R/ X5R/Y5V)of the rated voltage is applied between the terminations fo 1 to 5 seconds, provided the charge /discharge current is less than 500mA 7. Temperature Coefficient of Capacitance Dielectrics Specification Testing Condition Measure capacitance under follow table list temperature: STEP NPO, X7R X5R Y5V 1 25 ±2 25 ±2 25 ±2 NPO Temperature coefficient within ±30ppm/℃ Cp drift within ±0.2% or ±0.05pF 2 -55±3 -55±3 -30±3 X7R/X5R Capacitance change within ±15% 3 4 5 25 ±2 125±3 25 ±2 25 ±2 85±3 25 ±2 25 ±2 85±3 25 ±2 Y5V Capacitance change within +22%, -82% 1) NPO The capacitance drift is calculated by dividing the differences between the maximum and minimum measured values in the step 1,3 and 5. The temperature coefficient is determined using the Capacitance measured in step 3 as a reference. 2) X7R ,X5R and Y5V The ranges of capacitance change compared within the above 25℃ value over the temperature ranges shall be within the specified ranges. Suntan ® Technology Company Limited Website: www.suntan.com.hk Email: info@suntan.com.hk Tel: (852) 8202 8782 Fax: (852) 8208 6246 |
Nº de peça semelhante - TS18_17 |
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Descrição semelhante - TS18_17 |
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