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AD7142 Folha de dados(PDF) 40 Page - Analog Devices |
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AD7142 Folha de dados(HTML) 40 Page - Analog Devices |
40 / 70 page AD7142 Data Sheet Rev. B | Page 40 of 70 REGISTER MAP The AD7142 address space is divided into three different register banks, referred to as Bank 1, Bank 2, and Bank 3. Figure 59 shows the division of these three banks. Bank 1 contains control registers, CDC conversion control registers, interrupt enable registers, interrupt status registers, CDC 16-bit conversion data registers, device ID registers, and proximity status registers. Bank 2 contains the configuration registers used for uniquely configuring the CIN inputs for each conversion stage. Initialize the Bank 2 configuration registers immediately after power-up to obtain valid CDC conversion result data. Bank 3 registers contain the results of each conversion stage. These registers automatically update at the end of each conversion sequence. Although these registers are primarily used by the AD7142 internal data processing, they are accessible by the host processor for additional external data processing, if desired. Default values are undefined for Bank 2 registers and Bank 3 registers until after power-up and configuration of the Bank 2 registers. REGISTER BANK 1 ADDR 0x000 ADDR 0x018 ADDR 0x001 ADDR 0x005 ADDR 0x008 ADDR 0x00B ADDR 0x017 ADDR 0x7F0 SET UP CONTROL (1 REGISTER) CALIBRATION AND SET UP (4 REGISTERS) INTERRUPT ENABLE (3 REGISTERS) INTERRUPT STATUS (3 REGISTERS) CDC 16-BIT CONVERSION DATA (12 REGISTERS) DEVICE ID REGISTER INVALID DO NOT ACCESS REGISTER BANK 2 ADDR 0x080 ADDR 0x0B8 ADDR 0x088 ADDR 0x090 ADDR 0x098 ADDR 0x0A0 ADDR 0x0A8 ADDR 0x0B0 ADDR 0x0C8 ADDR 0x0C0 ADDR 0x0D8 ADDR 0x0D0 REGISTER BANK 3 ADDR 0xE0 ADDR 0x1DC ADDR 0x104 ADDR 0x128 ADDR 0x14C ADDR 0x170 ADDR 0x194 ADDR 0x1B8 ADDR 0x224 ADDR 0x200 ADDR 026C ADDR 0x248 PROXIMITY STATUS REGISTER ADDR 0x042 INVALID DO NOT ACCESS ADDR 0x043 STAGE11 CONFIGURATION (8 REGISTERS) STAGE10 CONFIGURATION (8 REGISTERS) STAGE9 CONFIGURATION (8 REGISTERS) STAGE8 CONFIGURATION (8 REGISTERS) STAGE7 CONFIGURATION (8 REGISTERS) STAGE6 CONFIGURATION (8 REGISTERS) STAGE5 CONFIGURATION (8 REGISTERS) STAGE4 CONFIGURATION (8 REGISTERS) STAGE3 CONFIGURATION (8 REGISTERS) STAGE2 CONFIGURATION (8 REGISTERS) STAGE1 CONFIGURATION (8 REGISTERS) STAGE0 CONFIGURATION (8 REGISTERS) STAGE0 RESULTS (36 REGISTERS) STAGE1 RESULTS (36 REGISTERS) STAGE2 RESULTS (36 REGISTERS) STAGE3 RESULTS (36 REGISTERS) STAGE4 RESULTS (36 REGISTERS) STAGE5 RESULTS (36 REGISTERS) STAGE6 RESULTS (36 REGISTERS) STAGE7 RESULTS (36 REGISTERS) STAGE8 RESULTS (36 REGISTERS) STAGE9 RESULTS (36 REGISTERS) STAGE10 RESULTS (36 REGISTERS) STAGE11 RESULTS (36 REGISTERS) Figure 59. Layout of Bank 1 Registers, Bank 2 Registers, and Bank 3 Registers |
Nº de peça semelhante - AD7142_17 |
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Descrição semelhante - AD7142_17 |
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