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AD7143 Folha de dados(PDF) 42 Page - Analog Devices

Nome de Peças AD7143
Descrição Electrónicos  Programmable Controller for Capacitance Touch Sensors
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

AD7143 Folha de dados(HTML) 42 Page - Analog Devices

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AD7143
Rev. 0 | Page 41 of 56
Table 25. STAGE_HIGH_LIMIT_INT Register1
Address
Data Bit
Default
Type
Name
Description
0x009
[0]
0
R
STAGE0_HIGH_LIMIT_INT
STAGE0 CDC conversion high limit interrupt result
1 indicates STAGE0_HIGH_THRESHOLD value exceeded
[1]
0
STAGE1_HIGH_LIMIT_INT
STAGE1 CDC conversion high limit interrupt result
1 indicates STAGE1_HIGH_THRESHOLD value exceeded
[2]
0
STAGE2_HIGH_LIMIT_INT
Stage2 CDC conversion high limit interrupt result
1 indicates STAGE2_HIGH_THRESHOLD value exceeded
[3]
0
STAGE3_HIGH_LIMIT_INT
STAGE3 CDC conversion high limit interrupt result
1 indicates STAGE3_HIGH_THRESHOLD value exceeded
[4]
0
STAGE4_HIGH_LIMIT_INT
STAGE4 CDC conversion high limit interrupt result
1 indicates STAGE4_HIGH_THRESHOLD value exceeded
[5]
0
STAGE5_HIGH_LIMIT_INT
STAGE5 CDC conversion high limit interrupt result
1 indicates STAGE5_HIGH_THRESHOLD value exceeded
[6]
0
STAGE6_HIGH_LIMIT_INT
STAGE6 CDC conversion high limit interrupt result
1 indicates STAGE6_HIGH_THRESHOLD value exceeded
[7]
0
STAGE7_HIGH_LIMIT_INT
STAGE7 CDC conversion high limit interrupt result
1 indicates STAGE7_HIGH_THRESHOLD value exceeded
[15:8]
Unused
Set unused register bits = 0
1 Registers self-clear to 0 after readback, provided that the limits are not exceeded.
Table 26. STAGE_COMPLETE_LIMIT_INT Register1
Address
Data Bit
Default
Type
Name
Description
0x00A
[0]
0
R
STAGE0_COMPLETE_STATUS_INT
STAGE0 conversion complete register interrupt status
1 indicates STAGE0 conversion completed
[1]
0
STAGE1_COMPLETE_STATUS_INT
STAGE1 conversion complete register interrupt status
1 indicates STAGE0 conversion completed
[2]
0
STAGE2_COMPLETE_STATUS_INT
STAGE2 conversion complete register interrupt status
1 indicates STAGE0 conversion completed
[3]
0
STAGE3_COMPLETE_STATUS_INT
STAGE3 conversion complete register interrupt status
1 indicates STAGE0 conversion completed
[4]
0
STAGE4_COMPLETE_STATUS_INT
STAGE4 conversion complete register interrupt status
1 indicates STAGE0 conversion completed
[5]
0
STAGE5_COMPLETE_STATUS_INT
STAGE5 conversion complete register interrupt status
1 indicates STAGE0 conversion completed
[6]
0
STAGE6_COMPLETE_STATUS_INT
STAGE6 conversion complete register interrupt status
1 indicates STAGE0 conversion completed
[7]
0
STAGE7_COMPLETE_STATUS_INT
STAGE7 conversion complete register interrupt status
1 indicates STAGE0 conversion completed
[15:8]
0
Unused
1 Registers self-clear to 0 after readback, provided that the limits are not exceeded.


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