AD7879_17 datasheet(23/40 Pages) AD

Nome de Peças	AD7879

Descrição Electrónicos	Low Voltage Controller for Touch Screens

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Fabricante Electrônico	AD [Analog Devices]

Página de início	http://www.analog.com

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Data Sheet

AD7879/AD7889

Rev. D | Page 23 of 40

Table 13. Control Register 2

Address

Bit Name

Data Bit

Description

Default Value

0x02

PM[1:0]

[15:14]

ADC power management.

0x4040

00 = full shutdown; the ADC, oscillator, bias, and temperature sensor are all powered

down.

01 = analog blocks to be powered down depend on the ADC mode.

If ADC mode is master mode, the ADC, oscillator, bias, and temperature sensor are

powered down and must wake up when the user touches the screen.

If ADC mode is slave mode, the ADC and temperature sensor are powered down

when not being used. They wake up automatically when required. The oscillator and

bias are powered up because they are needed to measure time. This also applies to the

single-conversion mode.

10 = ADC, bias, and oscillator are powered up continuously, irrespective of ADC mode.

11 = same as 01.

GPIO EN

13

GPIO enable.

0 = AUX/VBAT channel active.

1 = GPIO enabled on AUX/VBAT/GPIO pin.

GPIO DAT

12

GPIO data bit.

GPIO DIR

11

GPIO direction.

0 = output.

1 = input.

GPIO POL

10

GPIO polarity.

0 = GPIO pin is active low.

1 = GPIO pin is active high.

SER/DFR

9

Selects normal (single-ended) or ratiometric (differential) conversion.

0 = ratiometric (differential).

1 = normal (single-ended).

AVG[1:0]

[8:7]

ADC averaging.

00 = 2 middle values averaged (one measurement when median filter is disabled).

01 = 4 middle values averaged.

10 = 8 middle values averaged.

11 = 16 values averaged.

MED[1:0]

[6:5]

Median filter size.

00 = median filter disabled.

01 = 4 measurements.

10 = 8 measurements.

11 = 16 measurements.

SW/RST

4

Software reset; digital logic is reset when this bit is set.

FCD[3:0]

[3:0]

ADC first conversion delay.1

Starts at 128 µs (default) and continues to 4.096 ms in steps of 128 µs (see Table 22).

1 This delay occurs before conversion of the X and Y coordinate channels (including Z1 and Z2) to allow screen settling and before the first conversion to allow the ADC

to power up.

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